Banana Pi M3 LPDDR3 issues

Banana Pi SBCs design BPI-M3(A83T/R18)
1

Hi, I was going through the Bannan PI M3 schematic. In the LPDDR3 interface DDQS 1 & 2 and DM1 &2 are swapped. but not the Data lines. Why this changes are required? is there any reason?

Thanks and Regards, Sankar.K