I connected a JLink Edu to the jtag pins on the board. I could not figure out where to connect the JLink “nTRST” or “RESET” pin to the board. I did connect the JLink Edu to the board using the following pins:
gpio pin signal
==== === ======
1 vcc
6 gnd
gpio_70 7 tdi
gpio_71 11 tms
gpio_72 13 tck
gpio_73 15 tdo
I created an openocd configuration file called “spacemit.tcl” that has the following lines:
When I used the file with openocd I got the following error message:
Info : J-Link V11 compiled Mar 14 2024 13:16:08
Info : Hardware version: 11.00
Info : VTarget = 3.283 V
Info : clock speed 4000 kHz
Info : JTAG tap: k1x.cpu tap/device found: 0x08501c0d (mfg: 0x606 (Shenzhen Chixingzhe Technology Co Ltd), part: 0x8501, ver: 0x0)
Error: IR capture error at bit 5, saw 0x01 not 0x…3
Warn : Bypassing JTAG setup events due to errors
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Warn : target k1x.cpu0 examination failed
Info : starting gdb server for k1x.cpu0 on 3333
<<
Do you have an openocd configuration file that works with the board?
Thanks for your help.
I tried using the openocd configuration file with my jlink edu attached to the board:
I got a lot of error messages like:
Error: unable to halt hart 2
Error: dmcontrol=0x00020001
Error: dmstatus =0x004030a2
Error: Fatal: Hart 2 failed to halt during examine()
Warn : target riscv.cpu.2 examination failed
Info : datacount=2 progbufsize=2
Error: unable to halt hart 3
Error: dmcontrol=0x00030001
Error: dmstatus =0x004030a2
Error: Fatal: Hart 3 failed to halt during examine()
Warn : target riscv.cpu.7 examination failed
Info : starting gdb server for riscv.cpu.0 on 1024
Info : Listening on port 1024 for gdb connections
Error: Hart 1 is unavailable.
Error: Hart 2 is unavailable.
Error: Hart 3 is unavailable.
Maybe this is because I did not know where to connect the jlink ntrst pin or the RESET pin?
I got these messages using openocd. How do I allow reading and writing to CSRs?
Info : Disabling abstract command reads from CSRs.
Info : Disabling abstract command reads from CSRs.
Info : [riscv.cpu.0] Found 8 triggers
Info : Disabling abstract command writes to CSRs.
Hi @bwooster0,
To enable Jtag debugger on BFI-F3, do I need to switch SW5. On my side, after switching SW 5, board displayed an error related to IO device setup.