SpacemiT K1 8 core RISC-V chip (Banana Pi BPI-F3) RISC-V IME set Specification public on github
RISC-V IME set Specification
Introduction
This is a matrix extension proposal under the RISC-V IME extension standard. It has the following features.
- Low lost
- Reuse the vector registers and the related CSRs.
- Compatibility
- Support VLEN of vector registers from 128 bit to 4096 bit
- Almost binary portability
- Rich data types
- Integer int4/int8/int16
- float fp4/fp8/fp16/bf16
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