MT7623 overcloking, voltages, powerconsumption, governors

Banana Pi Router design
1

Hello I’m trying to overclock bpi R2 board to get more speed. I have installed heatsink to CPU.

This say up to 1.6Ghz is posible if 28nm:

ARM Developer

So my goal is to get it 1.7Ghz without fans… :wink:

I found that in some A7 core voltages is defined:

        opp@1400000000 {
                opp-hz = /bits/ 64 <1400000000>;
                opp-microvolt = <1250000>;
                clock-latency-ns = <140000>;
        };

In mt7623.dtsi it ends 1.3Ghz and 1.3v. Voltages rising fast in last Mhz, in 1.2Mhz they are 1.2v. How tight this is? Have anybody tested overclocking or other voltages?

Btw in gernamy if wattage is too much then can use “ondemand” governor to drop Mhz’s & voltages when idle. Frank have you measured power with “ondemand” governor?

Related files:

cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_available_frequencies
cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_max_freq
cat /sys/devices/system/cpu/cpu*/cpufreq/cpuinfo_cur_freq
cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_governor    (this is writable: echo ondemand > )
cat /sys/class/thermal/thermal_zone0/temp
2

Have not tried it…if it is safe (overheating) i can try it. What are min/max values for ondemand mode?

3

I think it uses values between:

/sys/devices/system/cpu/cpu*/cpufreq/scaling_available_frequencies

For normal kernels it reduce power consumption and so cpu runs cooler.

4

Just tryed to reduce CPU voltage at 1.3Ghz to 1.2v. Kernel atleast boot. Have not yet done test under load.

            opp-1300000000 {
                    opp-hz = /bits/ 64 <1300000000>;
                    opp-microvolt = <1200000>;
            };

cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
1300000

Overcloking dosn’t seems to be easy, tryed to add 1.4Ghz:

cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
98000 198000 398000 598000 747500 1040000 1196000 1300000 1400000 
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq             
1040000
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq 
1400000

1.5Ghz, got:

[    4.963686] cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 1040000 KHz
[    4.971219] cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed to: 1500000 KHz
but
cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
1040000

Hmm, there is in mediatek-cpufreq.c #define MAX_VOLT_LIMIT (1150000)

So atleast we now know why it drops to 1040000…

And if it was whole time 1.15v at 1.3Ghz and mfger thinks 1.3v is ok, then there is plenty of room to oc it…

5

There seems that cpufreq lowlevel driver is broken. I put printk’s in every function and got:

[    4.952468] cpufeqdev: asked mtk_cpufreq_driver_init
[    4.957787] cpufeqdev: asked mtk_cpufreq_probe
[    4.962212] cpufreqdev: asked mtk_cpu_dvfs_info_lookup 0
[    4.985780] cpufreqdev: asked mtk_cpu_dvfs_info_lookup 1
[    4.991065] cpufreqdev: asked mtk_cpu_dvfs_info_lookup 2
[    4.996372] cpufreqdev: asked mtk_cpu_dvfs_info_lookup 3
[    5.001711] cpufeqdev: asked mtk_cpufreq_init
[    5.006053] cpufreqdev: asked mtk_cpu_dvfs_info_lookup 0
[    5.011418] cpufeqdev: asked mtk_cpufreq_ready
[   36.370190] cpufreq: notification 0 of frequency transition to 1400000 kHz
[   36.370225] cpufreqdrv: set_target oldwas: hz:1040000000 vproc:1150000
[   36.370236] cpufreqdrv: set_target newis: hz:1400000000 vproc:1150000
[   36.370345] cpufreq: notification 1 of frequency transition to 1400000 kHz
[  203.198821] cpufreq: notification 0 of frequency transition to 1040000 kHz
[  203.198838] cpufreq: notification 1 of frequency transition to 1040000 kHz
[  203.198951] cpufreq: notification 0 of frequency transition to 1400000 kHz
[  203.198977] cpufreqdrv: set_target oldwas: hz:1040000000 vproc:1150000
[  203.198988] cpufreqdrv: set_target newis: hz:1400000000 vproc:1150000
[  203.199053] cpufreq: notification 1 of frequency transition to 1400000 kHz
[  203.199374] cpufreq: notification 0 of frequency transition to 1040000 kHz
[  203.199385] cpufreq: notification 1 of frequency transition to 1040000 kHz
[  203.199469] cpufreq: notification 0 of frequency transition to 1400000 kHz
[  203.199496] cpufreqdrv: set_target oldwas: hz:1040000000 vproc:1150000
[  203.199506] cpufreqdrv: set_target newis: hz:1400000000 vproc:1150000
[  203.199566] cpufreq: notification 1 of frequency transition to 1400000 kHz
[  203.199748] cpufreq: notification 0 of frequency transition to 1040000 kHz
[  203.199757] cpufreq: notification 1 of frequency transition to 1040000 kHz
[  203.199874] cpufreq: notification 0 of frequency transition to 1400000 kHz
[  203.199898] cpufreqdrv: set_target oldwas: hz:1040000000 vproc:1150000
[  203.199907] cpufreqdrv: set_target newis: hz:1400000000 vproc:1150000
[  203.199963] cpufreq: notification 1 of frequency transition to 1400000 kHz
[  203.200147] cpufreq: notification 0 of frequency transition to 1040000 kHz
[  203.200158] cpufreq: notification 1 of frequency transition to 1040000 kHz
[  203.200220] cpufreq: notification 0 of frequency transition to 1400000 kHz
[  203.200243] cpufreqdrv: set_target oldwas: hz:1040000000 vproc:1150000
[  203.200252] cpufreqdrv: set_target newis: hz:1400000000 vproc:1150000
[  203.200311] cpufreq: notification 1 of frequency transition to 1400000 kHz

So it try to set new frequency&voltage, reports they are fine, but actually they are not adjusted. Need to dig deeper where broblem is.

Hmm, clk-mt7623.c is missing and it compiles all clk-chips. Strange:

drivers/clk/mediatek/clk-apmixed.o     drivers/clk/mediatek/clk-mt2701-img.o   drivers/clk/mediatek/clk-mt8173.o
drivers/clk/mediatek/clk-cpumux.o      drivers/clk/mediatek/clk-mt2701-mm.o    drivers/clk/mediatek/clk-mtk.o
drivers/clk/mediatek/clk-gate.o        drivers/clk/mediatek/clk-mt2701.o       drivers/clk/mediatek/clk-pll.o
drivers/clk/mediatek/clk-mt2701-eth.o  drivers/clk/mediatek/clk-mt2701-vdec.o  drivers/clk/mediatek/reset.o
drivers/clk/mediatek/clk-mt2701-g3d.o  drivers/clk/mediatek/clk-mt7622.o
drivers/clk/mediatek/clk-mt2701-hif.o  drivers/clk/mediatek/clk-mt8135.o

This is also intresting: grep -R 7623 drivers/clk/mediatek/*

So there is not mt7623 spesific data at all. Only mt2701.

Wonder why:

  CC      drivers/clk/mediatek/clk-mt7622.o

7622 is 64bit 2cpu. It should not include in kernel…?

6

Mt7623 contains most functions (clock,pinctrl,…) from mt2701…

7

Jep, seems to use it:

[    0.426744] clk: asked mt2701 clk_mt2701_probe
[    0.426778] clk: asked mt2701 mtk_topckgen_init
[    0.456275] clk: asked mt2701 clk_mt2701_probe
[    0.456309] clk: asked mt2701 mtk_infrasys_init
[    0.463809] clk: asked mt2701 clk_mt2701_probe
[    0.463838] clk: asked mt2701 mtk_pericfg_init
[    0.496848] clk: asked mt2701 clk_mt2701_probe

[   36.408197] cpufreqdrv: set_target oldwas: hz:1040000000 vproc:1150000
[   36.408209] cpufreqdrv: set_target newis: hz:1400000000 vproc:1149000
[   36.408212] cpufreqdrv: set_target targetVis: 1149000
[   36.408215] cpufreqdrv: set_target skipped vprocset because target_vproc:1149000
[   36.408279] cpufreqdrv: clk_set_parent return: 0
[   36.408284] clk: clk_set_rate asked: 1400000000 
[   36.408328] cpufreqdrv: clk_set_rate 1400000000 return: 0
[   36.408336] cpufreqdrv: clk_set_parent return: 0

So need to dig clk.c more deeper. However it dosn’t drop mt2701 level.

8

It seems to clk_set_rate() spawns two times subfunctions and dosn’t indicate failure but actual Mhz’s dosn’t change:

[   34.043407] cpufreq: notification 0 of frequency transition to 1400000 kHz
[   34.043441] cpufreqdrv: set_target oldwas: hz:1300000000 vproc:1150000
[   34.043452] cpufreqdrv: set_target newis: hz:1400000000 vproc:1149000
[   34.043455] cpufreqdrv: set_target targetVis: 1149000
[   34.043458] cpufreqdrv: set_target skipped vprocset because target_vproc:1149000
[   34.043476] cpufreqdrv: clk_set_parent return: 0
[   34.043480] clk: clk_set_rate asked: 1400000000 
[   34.043484] clk: asked clk_core_set_rate_nolock 1400000000 
[   34.043492] clk: round_new_rate: 1399999390 
[   34.043499] clk: clk_pm_runtime returned: 0
[   34.043503] clk: asked clk_change_rate, oldrate 1300000000
[   34.043536] clk: asked clk_change_rate, oldrate 1300000000
[   34.043539] clk: clk_change_rate ends
[   34.043541] clk: clk_change_rate ends
[   34.043544] clk: changed rate to 1400000000 
[   34.043549] cpufreqdrv: clk_set_rate 1400000000 return: 0
[   34.043556] cpufreqdrv: clk_set_parent return: 0
[   34.043559] cpufreqdrv: set_vproc: 1149000
[   34.043564] cpufreqdrv: finished function
[   34.043567] cpufreq: notification 1 of frequency transition to 1400000 kHz

clk.c seems to be broken. It is writed style “I’ll keep my job”, so difficult to debug. Look:

[   33.223086] cpufreq: notification 0 of frequency transition to 1400000 kHz
[   33.223121] cpufreqdrv: set_target oldwas: hz:1300000000 vproc:1150000
[   33.223131] cpufreqdrv: set_target newis: hz:1400000000 vproc:1150000
[   33.223134] cpufreqdrv: set_target targetVis: 1150000
[   33.223138] cpufreqdrv: set_target skipped vprocset because target_vproc:1150000
[   33.223140] clk: asked clk_set_parent 
[   33.223143] clk: asked clk_core_set_parent_nolock 
[   33.223148] clk: clk_core_set_parent_nolock p_rate: 1092000000 
[   33.223152] clk: clk_core_set_parent_nolock speculate_rates ret: 0 
[   33.223166] clk: clk_core_set_parent_nolock set_parent ret: 0 
[   33.223169] clk: clk_core_set_parent_nolock ends 
[   33.223172] clk: clk_set_parent clk_core_set_parent_nolock ret: 0 
[   33.223176] cpufreqdrv: clk_set_parent return: 0
[   33.223179] clk: clk_set_rate asked: 1400000000 
[   33.223183] clk: asked clk_core_set_rate_nolock 1400000000 
[   33.223191] clk: round_new_rate: 1399999390 
[   33.223198] clk: clk_pm_runtime returned: 0
[   33.223203] clk: asked clk_change_rate, oldrate 1300000000
[   33.223206] clk: clk_change_rate, new_parent bestrate 26000000
[   33.223238] clk: asked clk_change_rate, oldrate 1300000000
[   33.223241] clk: clk_change_rate, cur_parent bestrate 1300000000
[   33.223244] clk: clk_change_rate ends
[   33.223247] clk: clk_change_rate ends
[   33.223250] clk: changed rate to 1400000000 
[   33.223254] cpufreqdrv: clk_set_rate 1400000000 return: 0
[   33.223257] clk: asked clk_set_parent 
[   33.223259] clk: asked clk_core_set_parent_nolock 
[   33.223262] clk: clk_core_set_parent_nolock p_rate: 1300000000 
[   33.223266] clk: clk_core_set_parent_nolock speculate_rates ret: 0 
[   33.223271] clk: clk_core_set_parent_nolock set_parent ret: 0 
[   33.223273] clk: clk_core_set_parent_nolock ends 
[   33.223275] clk: clk_set_parent clk_core_set_parent_nolock ret: 0 
[   33.223278] cpufreqdrv: clk_set_parent return: 0
[   33.223280] cpufreqdrv: finished function
[   33.223284] cpufreq: notification 1 of frequency transition to 1400000 kHz
9

How about this, is it ok??

[   17.444317] [drm:mtk_drm_crtc_atomic_enable] mtk_crtc_ddp_hw_init
[   17.444332] [drm:mtk_drm_crtc_atomic_enable] mtk_crtc_ddp_clk_enable
[   17.444343] [drm:mtk_drm_crtc_atomic_enable] mediatek_ddp_ddp_path_setup
[   17.444414] clk: clk_set_rate asked: 864000000 
[   17.444417] clk: asked clk_core_set_rate_nolock 864000000 
[   17.444426] clk: round_new_rate: 863999329 
[   17.444441] clk: clk_pm_runtime returned: 0
[   17.444445] clk: asked clk_change_rate, oldrate 148499848
[   17.444448] clk: clk_change_rate, new_parent bestrate 26000000
[   17.444478] clk: asked clk_change_rate, oldrate 148499848
[   17.444480] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444483] clk: asked clk_change_rate, oldrate 0
[   17.444485] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444504] clk: asked clk_change_rate, oldrate 0
[   17.444506] clk: clk_change_rate, cur_parent bestrate 0
[   17.444508] clk: asked clk_change_rate, oldrate 0
[   17.444510] clk: clk_change_rate, cur_parent bestrate 0
[   17.444512] clk: asked clk_change_rate, oldrate 0
[   17.444514] clk: clk_change_rate, cur_parent bestrate 0
[   17.444516] clk: clk_change_rate ends
[   17.444517] clk: clk_change_rate ends
[   17.444519] clk: clk_change_rate ends
[   17.444521] clk: asked clk_change_rate, oldrate 0
[   17.444523] clk: clk_change_rate, cur_parent bestrate 0
[   17.444524] clk: clk_change_rate ends
[   17.444526] clk: asked clk_change_rate, oldrate 0
[   17.444528] clk: clk_change_rate, cur_parent bestrate 0
[   17.444530] clk: clk_change_rate ends
[   17.444531] clk: clk_change_rate ends
[   17.444533] clk: clk_change_rate ends
[   17.444535] clk: asked clk_change_rate, oldrate 148499848
[   17.444537] clk: clk_change_rate, new_parent bestrate 863999329
[   17.444540] clk: asked clk_change_rate, oldrate 148499848
[   17.444542] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444544] clk: asked clk_change_rate, oldrate 148499848
[   17.444546] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444548] clk: clk_change_rate ends
[   17.444550] clk: asked clk_change_rate, oldrate 148499848
[   17.444552] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444554] clk: clk_change_rate ends
[   17.444555] clk: clk_change_rate ends
[   17.444557] clk: asked clk_change_rate, oldrate 148499848
[   17.444560] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444562] clk: asked clk_change_rate, oldrate 148499848
[   17.444564] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444566] clk: clk_change_rate ends
[   17.444568] clk: asked clk_change_rate, oldrate 148499848
[   17.444570] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444572] clk: clk_change_rate ends
[   17.444573] clk: clk_change_rate ends
[   17.444575] clk: clk_change_rate ends
[   17.444577] clk: asked clk_change_rate, oldrate 74249924
[   17.444579] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444581] clk: asked clk_change_rate, oldrate 74249924
[   17.444583] clk: clk_change_rate, cur_parent bestrate 431999664
[   17.444586] clk: asked clk_change_rate, oldrate 74249924
[   17.444588] clk: clk_change_rate, cur_parent bestrate 431999664
[   17.444589] clk: clk_change_rate ends
[   17.444591] clk: clk_change_rate ends
[   17.444592] clk: clk_change_rate ends
[   17.444594] clk: asked clk_change_rate, oldrate 37124962
[   17.444597] clk: clk_change_rate, cur_parent bestrate 863999329
[   17.444598] clk: clk_change_rate ends
[   17.444600] clk: clk_change_rate ends
[   17.444602] clk: changed rate to 864000000 
[   17.444605] clk: clk_set_rate asked: 107999916 
[   17.444607] clk: asked clk_core_set_rate_nolock 107999916 
[   17.444635] clk: round_new_rate: 107999817 
[   17.444644] clk: clk_pm_runtime returned: 0
[   17.444647] clk: asked clk_change_rate, oldrate 863999329
[   17.444649] clk: clk_change_rate, new_parent bestrate 26000000
[   17.444676] clk: asked clk_change_rate, oldrate 863999329
[   17.444679] clk: clk_change_rate, cur_parent bestrate 107999817
[   17.444681] clk: asked clk_change_rate, oldrate 0
[   17.444683] clk: clk_change_rate, cur_parent bestrate 107999817
[   17.444701] clk: asked clk_change_rate, oldrate 0
[   17.444703] clk: clk_change_rate, cur_parent bestrate 0
[   17.444705] clk: asked clk_change_rate, oldrate 0
[   17.444707] clk: clk_change_rate, cur_parent bestrate 0
[   17.444709] clk: asked clk_change_rate, oldrate 0
[   17.444711] clk: clk_change_rate, cur_parent bestrate 0
[   17.444712] clk: clk_change_rate ends
[   17.444714] clk: clk_change_rate ends
[   17.444715] clk: clk_change_rate ends
[   17.444717] clk: asked clk_change_rate, oldrate 0
[   17.444719] clk: clk_change_rate, cur_parent bestrate 0
[   17.444721] clk: clk_change_rate ends
[   17.444723] clk: asked clk_change_rate, oldrate 0
[   17.444724] clk: clk_change_rate, cur_parent bestrate 0
[   17.444726] clk: clk_change_rate ends
[   17.444728] clk: clk_change_rate ends
[   17.444729] clk: clk_change_rate ends
[   17.444731] clk: asked clk_change_rate, oldrate 863999329
[   17.444733] clk: clk_change_rate, new_parent bestrate 107999817
[   17.444736] clk: asked clk_change_rate, oldrate 863999329
[   17.444738] clk: clk_change_rate, new_parent bestrate 107999817
[   17.444740] clk: asked clk_change_rate, oldrate 863999329
[   17.444742] clk: clk_change_rate, cur_parent bestrate 107999817
[   17.444744] clk: clk_change_rate ends
[   17.444746] clk: asked clk_change_rate, oldrate 863999329
[   17.444748] clk: clk_change_rate, new_parent bestrate 107999817
[   17.444750] clk: clk_change_rate ends
[   17.444751] clk: clk_change_rate ends
[   17.444754] clk: asked clk_change_rate, oldrate 863999329
[   17.444756] clk: clk_change_rate, cur_parent bestrate 107999817
[   17.444758] clk: asked clk_change_rate, oldrate 863999329
[   17.444760] clk: clk_change_rate, cur_parent bestrate 107999817
[   17.444762] clk: clk_change_rate ends
[   17.444764] clk: asked clk_change_rate, oldrate 863999329
[   17.444766] clk: clk_change_rate, cur_parent bestrate 107999817
[   17.444767] clk: clk_change_rate ends
[   17.444769] clk: clk_change_rate ends
[   17.444770] clk: clk_change_rate ends
[   17.444772] clk: asked clk_change_rate, oldrate 431999664
[   17.444775] clk: clk_change_rate, cur_parent bestrate 107999817
[   17.444777] clk: asked clk_change_rate, oldrate 431999664
[   17.444779] clk: clk_change_rate, cur_parent bestrate 53999908
[   17.444781] clk: asked clk_change_rate, oldrate 431999664
[   17.444783] clk: clk_change_rate, cur_parent bestrate 53999908
[   17.444785] clk: clk_change_rate ends
[   17.444786] clk: clk_change_rate ends
[   17.444788] clk: clk_change_rate ends
[   17.444790] clk: asked clk_change_rate, oldrate 215999832
[   17.444792] clk: clk_change_rate, cur_parent bestrate 107999817
[   17.444794] clk: clk_change_rate ends
[   17.444796] clk: clk_change_rate ends
[   17.444798] clk: changed rate to 107999916 
[   17.448864] clk: clk_set_rate asked: 108000000 
[   17.448867] clk: asked clk_core_set_rate_nolock 108000000 
[   17.448880] clk: round_new_rate: 108000000 
[   17.448891] clk: clk_pm_runtime returned: 0
[   17.448895] clk: asked clk_change_rate, oldrate 107999817
[   17.448897] clk: clk_change_rate, new_parent bestrate 26000000
[   17.448925] clk: asked clk_change_rate, oldrate 107999817
[   17.448927] clk: clk_change_rate, new_parent bestrate 107999917
[   17.448930] clk: asked clk_change_rate, oldrate 0
[   17.448932] clk: clk_change_rate, new_parent bestrate 107999917
[   17.448950] clk: asked clk_change_rate, oldrate 0
[   17.448953] clk: clk_change_rate, new_parent bestrate 108000000
[   17.448955] clk: asked clk_change_rate, oldrate 0
[   17.448957] clk: clk_change_rate, new_parent bestrate 108000000
[   17.448959] clk: asked clk_change_rate, oldrate 0
[   17.448961] clk: clk_change_rate, new_parent bestrate 108000000
[   17.448963] clk: clk_change_rate ends
[   17.448964] clk: clk_change_rate ends
[   17.448966] clk: clk_change_rate ends
[   17.448968] clk: asked clk_change_rate, oldrate 0
[   17.448970] clk: clk_change_rate, cur_parent bestrate 108000000
[   17.448971] clk: clk_change_rate ends
[   17.448973] clk: asked clk_change_rate, oldrate 0
[   17.448975] clk: clk_change_rate, cur_parent bestrate 108000000
[   17.448977] clk: clk_change_rate ends
[   17.448979] clk: clk_change_rate ends
[   17.448980] clk: clk_change_rate ends
[   17.448982] clk: asked clk_change_rate, oldrate 107999817
[   17.448984] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.448987] clk: asked clk_change_rate, oldrate 107999817
[   17.448989] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.448991] clk: asked clk_change_rate, oldrate 107999817
[   17.448993] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.448995] clk: clk_change_rate ends
[   17.448997] clk: asked clk_change_rate, oldrate 107999817
[   17.448999] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.449001] clk: clk_change_rate ends
[   17.449002] clk: clk_change_rate ends
[   17.449004] clk: asked clk_change_rate, oldrate 107999817
[   17.449007] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.449009] clk: asked clk_change_rate, oldrate 107999817
[   17.449011] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.449012] clk: clk_change_rate ends
[   17.449015] clk: asked clk_change_rate, oldrate 107999817
[   17.449017] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.449018] clk: clk_change_rate ends
[   17.449020] clk: clk_change_rate ends
[   17.449021] clk: clk_change_rate ends
[   17.449023] clk: asked clk_change_rate, oldrate 53999908
[   17.449026] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.449028] clk: asked clk_change_rate, oldrate 53999908
[   17.449030] clk: clk_change_rate, cur_parent bestrate 53999958
[   17.449032] clk: asked clk_change_rate, oldrate 53999908
[   17.449034] clk: clk_change_rate, cur_parent bestrate 53999958
[   17.449036] clk: clk_change_rate ends
[   17.449037] clk: clk_change_rate ends
[   17.449039] clk: clk_change_rate ends
[   17.449041] clk: asked clk_change_rate, oldrate 26999954
[   17.449043] clk: clk_change_rate, cur_parent bestrate 107999917
[   17.449045] clk: clk_change_rate ends
[   17.449046] clk: clk_change_rate ends
[   17.449048] clk: changed rate to 108000000
10

Hello,I tryed to figure out diffrent clocks board use and found there is hardware implemented two frequencymeters. So write some shellcode to use them to check clocks. There is approx 100 clocks but only some are used. Calibration constant may need fix better. Currently it is taken from 564Mhz clock. And running enviroment tests are not done. Version 0.01

mt7623-frq-meter.sh (9.3 KB)

It is little slow to run so output can direct to file and use that file to grep active Mhz like:

grep -B1 Mhz …/fq-data.txt | grep -v ready |grep -B1 Mhz

My board seems to have 41 active clocks (hdmi off)

Comments?

11

I guess we need info from bpi/mtk for this…

12

My frequencymeter implementation is functional. You can test it if are brave enough :wink:

And second tool reg2grep is almost finished to version 0.001. I had put to database only mt7623 clock datas, but it can/should be extend… Live machine value check is in todo. Sample:

./reg2grep.sh faxi_ck
____________________________________________________________________________
0x10000004 RW	 	DCM_CFG 	AXI Bus Clock DCM Control Register
   bit:     7	 	dcm_enable  	Enables hf_faxi_ck DCM   
	    1: Enable DCM  
   bit:   4:0	 	dcm_full_fsel	Selects hf_faxi_ck DCM clock  
        1xxxx: 	hd_faxi_ck = hf_faxi_ck 
        01xxx: 	hd_faxi_ck = hf_faxi_ck/2 
        001xx: 	hd_faxi_ck = hf_faxi_ck/4 
        0001x: 	hd_faxi_ck = hf_faxi_ck/8 
        00001: 	hd_faxi_ck =hf_faxi_ck/16  
        00000: 	hd_faxi_ck = hf_faxi_ck/32 
____________________________________________________________________________
0x10000040 RW	 	CLK_CFG_0 	Function Clock Selection Register 0 
   bit:     7	 	pdn_axi     	Turns off hf_faxi_ck   
	    1: Enable clock-off  
____________________________________________________________________________
0x10000104 RW	 	CLK_CFG_9 	Function clock selection register 9 
   bit: 21:16	 	ckgen_clk_sel	Selects f_fckgen_ck clock mux (not glitch free)   
           01: 	hf_faxi_ck   
           02: 	hd_faxi_ck   
./reg2grep.sh faxi_ck  5.00s user 4.50s system 245% cpu 3.866 total

Edit added live machine data grab:

____________________________________________________________________________
0x10000004 RW	 	DCM_CFG 	AXI Bus Clock DCM Control Register        
1  bit:     7	 	dcm_enable  	Enables hf_faxi_ck DCM   
            1: 	Enable DCM        
MEM:        0=0
1  bit:   4:0	 	dcm_full_fsel	Selects hf_faxi_ck DCM clock  
        1xxxx: 	hd_faxi_ck = hf_faxi_ck       
        01xxx: 	hd_faxi_ck = hf_faxi_ck/2       
        001xx: 	hd_faxi_ck = hf_faxi_ck/4       
        0001x: 	hd_faxi_ck = hf_faxi_ck/8       
        00001: 	hd_faxi_ck =hf_faxi_ck/16        
        00000: 	hd_faxi_ck = hf_faxi_ck/32       
MEM:    00000=0
____________________________________________________________________________
0x10000040 RW	 	CLK_CFG_0 	Function Clock Selection Register 0         
1  bit:     7	 	pdn_axi     	Turns off hf_faxi_ck   
            1: 	Enable clock-off        
MEM:        0=0
1  bit:     4	 	clk_axi_inv 	Inverts hf_faxi_ck clock phase  
            1: 	Enable phase inversion       
MEM:        0=0
1  bit:   2:0	 	clk_axi_sel 	Selects hf_faxi_ck clock mux  
            0: 	clk26m         
            1: 	syspll1_d2         
            2: 	syspll_d5         
            3: 	syspll1_d4         
            4: 	univpll_d5         
            5: 	univpll2_d2         
            6: 	dmpll_ck         
            7: 	dmpll_d2         
MEM:      001=1
____________________________________________________________________________
0x10000104 RW	 	CLK_CFG_9 	Function clock selection register 9         
2  bit: 21:16	 	ckgen_clk_sel	Selects f_fckgen_ck clock mux (not glitch free)   
           01: 	hf_faxi_ck   
           02: 	hd_faxi_ck   
MEM:      000=0

Hmm, intresting:

01: hf_faxi_ck 
CKGEN_FMETER clk: 1 result Mhz: 271.70
--
02: hd_faxi_ck 
CKGEN_FMETER clk: 2 result Mhz: 271.70

0x10000004 RW	 	DCM_CFG 	AXI Bus Clock DCM Control Register 
             bit:   4:0	 	dcm_full_fsel	Selects hf_faxi_ck DCM clock 
                00000: 	        hd_faxi_ck = hf_faxi_ck/32       
MEM:    00000=0

Mhz’s should differ 1/32, it is in its bootsettings 00000. Need to dig why dosn’t affect

Find also udocumented register about ckgen, maybe posible to get more clocks to ckgen meter??

0x1000030C RW	 	MBIST_CFG_1 	Debug monitor selection register 1         
1  bit:   6:4	 	ckgen_byte_sel	Selects TOPCKGEN debugging monitor      
            0: 	undocumented         
MEM:      000=0 --> 0: undocumented     

And this also:
0x10000108 RW	 	CLK_CFG_10 	Debug monitor clock selection register         
   bit: 19:16	 	clk_ckmon3_sel	Selects f_fckmon3_ck clock mux (not glitch free)       
           12: 	AD_MAIN_H156M_CK         
MEM:     0000=0 -->       
   bit:  11:8	 	clk_ckmon2_sel	Selects f_fckmon2_ck clock mux (not glitch free)       
           12: 	AD_MAIN_H156M_CK         
MEM:     0000=0 -->       
   bit:   3:0	 	clk_ckmon1_sel	Selects f_fckmon1_ck clock mux (not glitch free)       
           12: 	AD_MAIN_H156M_CK         
MEM:     0000=0 -->
13

Have currently not much time…and don’t want to overclock my r2 :slight_smile:

14

When find time then test… Frequencymeter dosn’t O’C machine. It measures&displays various clock’s on board. It is only information tool.

I’ll O’C my machine when figure out how it should done correctly, then debug how kernel set it and fix kernel to do what I want… FIrst information then deeds…

15

I didn’t get how to use it:

bpi-r2-gentoo ~/tests # ./mt7623-frq-meter.sh
please implement all needed tests and then clean returnvalue to 0
enviroment tests failed, can't continue

Is it (will it be) available for public?

16

It is in alpha state so look sources and change 1 to 0 when you are happy. But there are not any tests implemented yet and it is root program… So be carefull. Find also that some high clocks have divider block 256 so result should multiply 256. And there is poorly documented registers. It may be posible that more registers need tweak at it give more clocks. I don’t know yet enough.

reg2grep public yes posible but there is some issues about its database. It maybe illegal in some country’s because source is property of Mediatek (manual). In my country it is not illegal write down Mediatek data but some others it may be.

O’C seems to be bunch of undocumented registers and I don’t know yet what they are and how they should be set… I’ll probing board iobase but scripts run slowly. May take some days to complete small area. Kernel sources are not very helpfull.

17

It seems device do some software frequency hopping or I have not found correct registers at all. There is sample from one “slowly” changing registerset at 98mhz. Nice puzzle isnt it?

	FD70	F970	F970	F970	3000	0003	0030	0300	0080	002D	
	F96A	FD70	F970	FD70	3000	0003	0030	0300	0080	002D	
	F970	F970	FD70	F970	3000	0003	0030	0003	0080	002D	
	FD70	FD70	FD68	F970	0030	0300	0180	0003	0080	002D	
	FD70	F970	FD70	F970	0003	0030	0300	3000	0080	002D	
	F970	FD70	F970	F970	3000	0003	0030	0300	35A2	002D	
	FD70	F970	FD70	F972	0030	0003	0030	3000	15D2	002D	
	FD70	F970	FD70	F970	3000	0300	0300	3000	0080	012C	
	FD70	FD70	FD70	F970	0300	3000	0003	3000	0080	002D	
	F970	F970	F970	F970	0300	3000	0003	0030	0080	002D	
	F970	FD70	FD70	FD70	0003	0030	0300	3000	0080	002D	
	F972	F970	F970	F970	0300	3000	0003	0030	0080	002D	
	FD70	F970	FD70	F970	0003	0030	0300	3000	0080	002D	
	F970	FD70	FD73	FD6B	3000	0003	0030	0300	2129	002D	
	F970	FD70	FD70	FD70	0030	3000	0300	3000	0080	002D	
	FD70	FD70	F970	FD70	3000	0003	0030	0300	0080	002D	
	F970	FD72	F970	FD70	0300	3000	0003	0030	0080	002D	
	F970	F960	FD6B	F970	0003	0030	0300	3000	0080	002D	
	F970	F970	F970	F970	3000	0003	0030	0300	0080	002D	
	FD70	FD70	F970	FD70	0030	0300	3000	0003	0080	012C	
	F970	FD70	F970	F970	0030	0300	3000	0300	0080	002D	
	FD70	F970	F972	F970	0300	3000	0003	0030	0080	0088	
	FD70	F970	F970	F970	0003	0030	0300	3000	0080	002D	
	F970	F970	FD70	F970	0300	3000	0003	0030	0080	002D	
	F970	F970	FD70	F970	0300	3000	0003	0030	0080	002D	
	FD70	F970	FD70	F970	0003	3000	3000	0003	0080	002D	
	FD70	FD70	F970	FD70	0003	0030	0300	3000	0080	002D	
	F970	FD70	F970	F970	0003	0030	0300	3000	0080	002D	
	F970	FD70	FD70	F970	3000	0003	0030	0300	0080	002D	
	F970	FD70	F970	F970	0030	0300	0030	0030	0080	002D
18

I just got 2Ghz at 1.3v:

cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
2000000
cat /sys/class/thermal/thermal_zone0/temp
50603

and during compile kernel:
cat /sys/class/thermal/thermal_zone0/temp
56348

armpll div:1 pcw:1260307
1 Like
19

Any howtos/benchmarks? :slightly_smiling_face:

20

What bencmark utility you recommend to emerge?

95% is to do correct .dtsi. There may be some timing broblem. I got it working to adding printk’s to many places. There is also 2Ghz limitter in sources. It is posible to modify too but I have not done yet…

Direct howto is maybe something that Mediatek dosn’t like here?