How to enable rdinstret and rdcycle on BananaPi BPI-F3

Banana PI RISC-V Design BPI-F3(SpacemiT K1)
1

I am trying to do precise performance measurements on the F3.

RISC-V spec suggests to use rdtime, rdinstret and rdcycle CSRs for performance monitoring in userspace applications. The default setting of kernel disables rdinstret and rdcycle, only rdtime is working. I suspect from the documentation that mcountinhibit CSR needs to be cleared.

Is there a way to enable rdinstret and rdcycle ie. with kernel bootarg?

2

It may be because the start/stop counter (mcountinhibit register) is controlled by the perf framework. You can disable the CONFIG_RISCV_PMU and CONFIG_RISCV_PMU_SBI of Linux kernel config, and then you can use the instret and cycle counter in code.

3

thanks, that helps a lot