FM350-GL and BE14 finally works on BPI-R4

frank-w · November 9, 2025, 7:38am

Where is the source for this overlay? Do you only set status of pci2 to disabled?

paladzin · November 9, 2025, 10:52am

Yes, src - me =)

 /dts-v1/;
/plugin/;

/ {
    compatible = "bananapi,bpi-r4", "mediatek,mt7988";

    fragment@0 {
        target = <&pcie2>;
        __overlay__ {
            status = "disabled";
        };
    };
};

frank-w · November 9, 2025, 11:24am

You could convert it like this (imho much more readable) and upstream it with description why this is useful

https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/

paladzin · November 13, 2025, 4:15pm

Thanks for the advice, but I have absolutely no experience with this. Could I ask you to do this, if it’s not too much trouble, thank you!

frank-w · November 13, 2025, 4:53pm

Should look like something like this

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2023 MediaTek Inc.
 */

/dts-v1/;
/plugin/;

/ {
	compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
};

&{/soc/pcie@11280000} {
	status = "disabled";
};

Put in the directory where mt7988a.dtsi is and add line in Makefile to let it compile like in my patch above

edit: added overlay to my repo

Ernest_Crus · November 23, 2025, 11:27pm

Has anyone a compiled ready firmware, just to save time?

paladzin · November 25, 2025, 2:25pm

anavas · February 10, 2026, 3:12pm

Is there anyone already build with usb mode (fm-350-gl - HP version ) for the bpi-r4 2.5g version ?

KJ-Gamer · February 12, 2026, 4:18am

There’s a build shortly after this comment. [Banana BPI-R4] all related to MTK-SDK - #958 by darkeye - Community Builds, Projects & Packages - OpenWrt Forum

svy · July 26, 2026, 7:01pm

BPI-R4: PCIe resource conflict (Unaddressable device) and initialization failure with Fibocom FM350-GL (MT7988 / T700)

Description:

On Banana Pi BPI-R4 running OpenWrt (MediaTek Filogic 880 target, kernel 6.12), the Fibocom FM350-GL (MediaTek T700 5G modem, ID 14c3:4d75) fails to initialize properly when connected via PCIe.

While the device is detected by lspci, the kernel throws memory resource conflict errors during PCIe bridge initialization, preventing the driver from establishing communication.

Hardware & Environment:

Board: Banana Pi BPI-R4 (eMMC version)
Modem: Fibocom FM350-GL (MT7988/T700)
OS/Firmware: OpenWrt 25.12 (Kernel 6.12.94)

Kernel Logs (`dmesg` snippet):

Plaintext[ 8.065245] xhci-mtk 11200000.usb: supply vusb33 not found, using dummy regulator ... [ 20.354799] resource: Unaddressable device pcie@11280000 [mem 0x20200000-0x27ffffff] conflicts with [mem 0x21800000-0x21807fff] [ 20.366310] resource: Unaddressable device pcie@11280000 [mem 0x20200000-0x27ffffff] conflicts with [mem 0x20800000-0x20ffffff] [ 20.387189] mtk-pcie-gen3 11280000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11280c00 data 1

`lspci -nn` Output:

Plaintext0003:00:00.0 PCI bridge [0604]: MEDIATEK Corp. MT7988 PCI Express Host Bridge [Filogic 880] [14c3:7988] (rev 01) 0003:01:00.0 Cellular controller/modem [0d40]: MEDIATEK Corp. T700 5G Modem [5G Solution 5000] [14c3:4d75] (rev 01)

Steps to Reproduce:

Install Fibocom FM350-GL into the M.2 PCIe slot of BPI-R4.
Boot OpenWrt.
Check dmesg and lspci.

Expected Behavior:

The modem initializes successfully on the PCIe bus without memory region overlap/conflicts.

Actual Behavior:

Memory window collision occurs (resource: Unaddressable device ... conflicts with ...), and the modem remains unusable in PCIe mode.

moore · July 27, 2026, 1:58am

The memory range mem 0x20200000–0x27fffff is pre-reserved by the system for PCIe MMIO. It appears this region has already been occupied by other components in the system, causing a conflict when PCIe attempts to allocate this memory.

Please investigate the current system memory reservation status to identify which component is occupying mem 0x21800000–0x21807fff and mem 0x20800000–0x20ffffff.
Simultaneously, please determine the size of MMIO memory the PCIe EP (Endpoint) currently requires, covering both I/O and Memory types.

svy · July 27, 2026, 3:49am

Thanks for analyzing this. Here is the detailed breakdown of the system memory reservation and the Endpoint (EP) requirements based on /proc/iomem and lspci -v:

1. System Memory / proc/iomem Status: The ranges 20800000–20ffffff and 21800000–21807fff are not occupied by external system components. Instead, they are allocated inside the root bridge window 20200000–27ffffff (assigned to pcie@11280000) specifically for the modem endpoint (0003:01:00.0).

Here is the exact layout from /proc/iomem:

Plaintext20200000-27ffffff : pcie@11280000 20200000-20207fff : 0003:00:00.0 (PCI bridge) 20800000-20ffffff : 0003:01:00.0 (Modem non-prefetchable memory) 21800000-21807fff : 0003:01:00.0 (Modem prefetchable memory)

2. PCIe Endpoint (Fibocom FM350-GL / MT7988 T700) MMIO Requirements: According to lspci -v -s 0003:01:00.0, the modem requests the following memory resources:

BAR 0 (Prefetchable): size=32K (mapped at 21800000)
BAR 2 (Non-prefetchable): size=8M (mapped at 20800000)
BAR 4 (Prefetchable): size=8M (mapped at 21000000)

**3. Crucial Behavior Clue (Cold vs. Warm Initialization): It is very important to note that during cold initialization (the first power-on from a completely powered-off state), the modem registers successfully. The memory conflict and initialization failure occur specifically during warm initialization (reboots), suggesting an issue with how the mtk-pcie-gen3 driver or reset sequence handles state cleanup and re-initialization.

Summary: The total requested MMIO footprint by the endpoint is well within the 128MB host bridge window (20200000-27ffffff), yet the kernel throws “Unaddressable device… conflicts with…” during initialization. Could this be an issue with how the mtk-pcie-gen3 driver or the DTS sets up the window mapping/translation for this specific PCIe port?

moore · July 29, 2026, 6:29am

To further confirm and resolve this, we recommend conducting the following checks:

Check PERST# GPIO during Reboot: Please verify if the M.2 slot’s PERST# pin is actually asserted (pulled low) when the reboot command is issued. An incomplete hardware reset timing is the most common cause for warm boot PCIe failures. You can check this with an oscilloscope, or review the reset-gpios property in your Device Tree for pcie@11280000 to ensure the mtk-pcie-gen3 driver is toggling it correctly during the shutdown phase.
Compare PCIe Config Space (Cold vs. Warm): Please dump the raw hex values of the configuration space for both the Bridge and the Modem during cold and warm boots using: lspci -xxx -s 0003:00:00.0 and lspci -xxx -s 0003:01:00.0 We specifically need to check if the Bridge’s Memory Base/Limit registers are zeroed out or abnormal during a warm boot, and whether the Endpoint’s BAR registers are returning unexpected size values.
Test with pci=realloc Kernel Parameter: As a diagnostic workaround, please try adding pci=realloc to your kernel boot arguments (cmdline). This forces the kernel to ignore any residual BAR configurations and reallocate all resources from scratch. If the modem initializes successfully on warm boot with this parameter, it confirms the issue is caused by stale state misdirecting the kernel’s resource allocation algorithm.

svy · July 30, 2026, 7:49pm

Summary of Diagnostics.

Root Cause during Warm Reboot: During a warm reboot, the MediaTek Filogic 880 host controller and the T700 modem fail to reset their internal address translation descriptors and BAR registers. Upon re-initialization, the Linux kernel encounters a memory resource conflict "Unaddressable device... conflicts with..." because the endpoint’s previous state is not cleared. The hardware reset line` PERST# for the pcie@11280000 port is not defined as reset-gpios in the current Device Tree, preventing the host driver from toggling slot power or resetting the endpoint during reboots.
Hypothesis Validation (Runtime Fix): Manually removing and rescaning the PCI bus:

echo 1 > /sys/bus/pci/devices/0003:01:00.0/remove
echo 1 > /sys/bus/pci/rescan

Successfully brings the device back onto the bus (14c3:4d75), proving that physical traces, power, and the chip itself are entirely healthy. The issue is strictly software-sequential (the lack of an endpoint hardware reset during a warm reboot). Meanwhile, a cold boot or hardware reset successfully restores standard modem initialization without any errors.

Proposed Fix / Workaround:

Proper Fix: Add the slot reset line definition reset-gpios to the Device Tree DTS for the corresponding PCIe controller so that the mtk-pcie-gen3 driver performs a proper reset cycle PERST# during a warm reboot.
Workaround: Until the Device Tree includes the proper reset GPIO, reliable recovery from a reboot currently requires a cold boot (power cycle) rather than a soft warm reboot.

Summary: If the M.2 slot is intended for a cellular modem and the PERST# line is routed to a CPU GPIO pin, defining reset-gpios is essential to prevent freezing in fastboot mode and eliminate the need for hard power cycling during reboots.

compare

root@BPI-R4-emmc:~# cat /tmp/bridge_reset.hex 0003:00:00.0 PCI bridge: MEDIATEK Corp. MT7988 PCI Express Host Bridge [Filogic 880] (rev 01)

00: c3 14 88 79 06 04 10 00 01 00 04 06 00 00 01 00
10: 04 00 20 20 00 00 00 00 00 01 01 00 f1 01 00 00
20: 80 20 f0 20 01 21 b1 21 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 72 01 02 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 e0 42 00 21 80 00 00 3f 19 00 00 13 dc 79 01
90: 40 00 13 30 00 00 04 00 00 00 40 01 18 00 01 00
a0: 00 00 00 00 1f 08 10 00 00 04 00 00 0e 00 00 00
b0: 43 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 05 f8 8b 01 00 0c 28 11 00 00 00 00 00 00 00 00
f0: fe ff ff ff 00 00 00 00 01 00 03 c8 08 00 00 00

root@BPI-R4-emmc:~# cat /tmp/modem_reset.hex 0003:01:00.0 Cellular controller/modem: MEDIATEK Corp. T700 5G Modem [5G Solution 5000] (rev 01)

00: c3 14 75 4d 06 04 10 00 01 00 40 0d 00 00 00 00
10: 0c 00 80 21 00 00 00 00 04 00 80 20 00 00 00 00
20: 0c 00 00 21 00 00 00 00 00 00 00 00 f8 1c 00 35
30: 00 00 00 00 80 00 00 00 00 00 00 00 72 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 d0 02 00 e1 8f 00 00 3f 19 00 00 23 dc 45 01
90: 40 00 13 10 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 1f 08 10 00 00 04 00 00 0e 00 00 00
b0: 03 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 11 e0 21 80 00 40 00 00 80 0f 00 00 00 00 00 00
e0: 05 f8 8a 01 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 01 00 23 fe 08 00 00 00

root@BPI-R4-emmc:~# cat /tmp/bridge_warm.hex 0003:00:00.0 PCI bridge: MEDIATEK Corp. MT7988 PCI Express Host Bridge [Filogic 880] (rev 01)

00: c3 14 88 79 06 04 10 00 01 00 04 06 00 00 01 00
10: 04 00 20 20 00 00 00 00 00 01 01 00 f1 01 00 00
20: 80 20 f0 20 01 21 b1 21 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 72 01 02 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 e0 42 00 21 80 00 00 3f 19 00 00 13 dc 79 01
90: 40 00 13 30 00 00 04 00 00 00 40 01 18 00 01 00
a0: 00 00 00 00 1f 08 10 00 00 04 00 00 0e 00 00 00
b0: 43 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 05 f8 8b 01 00 0c 28 11 00 00 00 00 00 00 00 00
f0: fe ff ff ff 00 00 00 00 01 00 03 c8 08 00 00 00

root@BPI-R4-emmc:~# cat /tmp/modem_warm.hex 0003:01:00.0 Cellular controller/modem: MEDIATEK Corp. T700 5G Modem [5G Solution 5000] (rev 01)

00: c3 14 75 4d 06 04 10 00 01 00 40 0d 00 00 00 00
10: 0c 00 80 21 00 00 00 00 04 00 80 20 00 00 00 00
20: 0c 00 00 21 00 00 00 00 00 00 00 00 f8 1c 00 35
30: 00 00 00 00 80 00 00 00 00 00 00 00 72 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 d0 02 00 e1 8f 00 00 3f 19 00 00 23 dc 45 01
90: 40 00 13 10 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 1f 08 10 00 00 04 00 00 0e 00 00 00
b0: 03 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 11 e0 21 80 00 40 00 00 80 0f 00 00 00 00 00 00
e0: 05 f8 8a 01 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 01 00 23 fe 08 00 00 00

schematic

PERST# - 50 pin Reset - 67 pin

These circuit diagram sections are from rev 1.3. The BPI R4 V1.3 SCH Change list does not mention any changes regarding the current question about GPIO74. This is likely identical to rev1.1, on which the testing was conducted.

test gpio

root@BPI-R4-emmc:~# cat /sys/kernel/debug/gpio
gpiochip0: GPIOs 512-595, parent: platform/1001f000.pinctrl, pinctrl_moore:
 gpio-512 (                    |tx-disable          ) in  lo
 gpio-513 (                    |tx-fault            ) in  hi IRQ
 gpio-514 (                    |los                 ) in  hi IRQ
 gpio-515 (                    |rate-select0        ) in  hi ACTIVE LOW
 gpio-517 (                    |reset               ) out hi ACTIVE LOW
 gpio-526 (                    |WPS                 ) in  hi IRQ ACTIVE LOW
 gpio-533 (                    |rate-select0        ) in  lo ACTIVE LOW
 gpio-566 (                    |los                 ) in  hi IRQ
 gpio-575 (                    |blue:wps            ) out lo
 gpio-581 (                    |tx-fault            ) in  hi IRQ
 gpio-582 (                    |tx-disable          ) in  lo
 gpio-591 (                    |green:status        ) out hi
 gpio-594 (                    |mod-def0            ) in  hi IRQ ACTIVE LOW
 gpio-595 (                    |mod-def0            ) in  hi IRQ ACTIVE LOW
root@BPI-R4-emmc:~# grep 586 /sys/kernel/debug/gpio
root@BPI-R4-emmc:~# root@BPI-R4-emmc:~# cat /sys/kernel/debug/gpio
-ash: root@BPI-R4-emmc:~#: not found
root@BPI-R4-emmc:~# cat /sys/kernel/debug/gpio | grep "gpio-74"
root@BPI-R4-emmc:~#
root@BPI-R4-emmc:~# dmesg | grep -i pcie
[    0.000000] Kernel command line: console=ttyS0,115200n1 pci=pcie_bus_perf pci=realloc root=/dev/fit0 rootwait
[    0.018958] /soc/pcie@11280000: Fixed dependency cycle(s) with /soc/pcie@11280000/interrupt-controller
[    0.019053] /soc/pcie@11290000: Fixed dependency cycle(s) with /soc/pcie@11290000/interrupt-controller
[    0.019146] /soc/pcie@11300000: Fixed dependency cycle(s) with /soc/pcie@11300000/interrupt-controller
[    0.019235] /soc/pcie@11310000: Fixed dependency cycle(s) with /soc/pcie@11310000/interrupt-controller
[    0.076075] mtk-pcie-gen3 11280000.pcie: host bridge /soc/pcie@11280000 ranges:
[    0.076092] mtk-pcie-gen3 11280000.pcie: Parsing ranges property...
[    0.076105] mtk-pcie-gen3 11280000.pcie:       IO 0x0020000000..0x00201fffff -> 0x0020000000
[    0.076125] mtk-pcie-gen3 11280000.pcie:      MEM 0x0020200000..0x0027ffffff -> 0x0020200000
[    0.076218] mtk-pcie-gen3 11290000.pcie: host bridge /soc/pcie@11290000 ranges:
[    0.076229] mtk-pcie-gen3 11290000.pcie: Parsing ranges property...
[    0.076240] mtk-pcie-gen3 11290000.pcie:       IO 0x0028000000..0x00281fffff -> 0x0028000000
[    0.076252] mtk-pcie-gen3 11290000.pcie:      MEM 0x0028200000..0x002fffffff -> 0x0028200000
[    0.076270] /soc/pcie@11290000: Failed to get clk index: 0 ret: -517
[    0.076279] mtk-pcie-gen3 11290000.pcie: failed to get clocks
[    0.076343] mtk-pcie-gen3 11300000.pcie: host bridge /soc/pcie@11300000 ranges:
[    0.076354] mtk-pcie-gen3 11300000.pcie: Parsing ranges property...
[    0.076365] mtk-pcie-gen3 11300000.pcie:       IO 0x0030000000..0x00301fffff -> 0x0030000000
[    0.076376] mtk-pcie-gen3 11300000.pcie:      MEM 0x0030200000..0x0037ffffff -> 0x0030200000
[    0.076393] /soc/pcie@11300000: Failed to get clk index: 0 ret: -517
[    0.076401] mtk-pcie-gen3 11300000.pcie: failed to get clocks
[    0.076476] mtk-pcie-gen3 11310000.pcie: host bridge /soc/pcie@11310000 ranges:
[    0.076486] mtk-pcie-gen3 11310000.pcie: Parsing ranges property...
[    0.076497] mtk-pcie-gen3 11310000.pcie:       IO 0x0038000000..0x00381fffff -> 0x0038000000
[    0.076508] mtk-pcie-gen3 11310000.pcie:      MEM 0x0038200000..0x003fffffff -> 0x0038200000
[    0.076524] /soc/pcie@11310000: Failed to get clk index: 0 ret: -517
[    0.076532] mtk-pcie-gen3 11310000.pcie: failed to get clocks
[    1.936324] mtk-pcie-gen3 11280000.pcie: host bridge /soc/pcie@11280000 ranges:
[    1.943656] mtk-pcie-gen3 11280000.pcie: Parsing ranges property...
[    1.949922] mtk-pcie-gen3 11280000.pcie:       IO 0x0020000000..0x00201fffff -> 0x0020000000
[    1.958364] mtk-pcie-gen3 11280000.pcie:      MEM 0x0020200000..0x0027ffffff -> 0x0020200000
[    2.196509] mtk-pcie-gen3 11280000.pcie: set IO trans window[0]: cpu_addr = 0x20000000, pci_addr = 0x20000000, size = 0x200000
[    2.207899] mtk-pcie-gen3 11280000.pcie: set MEM trans window[1]: cpu_addr = 0x20200000, pci_addr = 0x20200000, size = 0x200000
[    2.219366] mtk-pcie-gen3 11280000.pcie: set MEM trans window[2]: cpu_addr = 0x20400000, pci_addr = 0x20400000, size = 0x400000
[    2.230832] mtk-pcie-gen3 11280000.pcie: set MEM trans window[3]: cpu_addr = 0x20800000, pci_addr = 0x20800000, size = 0x800000
[    2.242304] mtk-pcie-gen3 11280000.pcie: set MEM trans window[4]: cpu_addr = 0x21000000, pci_addr = 0x21000000, size = 0x1000000
[    2.253856] mtk-pcie-gen3 11280000.pcie: set MEM trans window[5]: cpu_addr = 0x22000000, pci_addr = 0x22000000, size = 0x2000000
[    2.265406] mtk-pcie-gen3 11280000.pcie: set MEM trans window[6]: cpu_addr = 0x24000000, pci_addr = 0x24000000, size = 0x4000000
[    2.277211] mtk-pcie-gen3 11280000.pcie: PCI host bridge to bus 0003:00
[    2.309843] pci 0003:00:00.0: [14c3:7988] type 01 class 0x060400 PCIe Root Port
[    2.390202] pci 0003:01:00.0: [14c3:4d75] type 00 class 0x0d4000 PCIe Endpoint
[    2.432828] pci 0003:01:00.0: 7.876 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x1 link at 0003:00:00.0 (capable of 15.752 Gb/s with 8.0 GT/s PCIe x2 link)
[    2.684444] pcieport 0003:00:00.0: assign IRQ: got 114
[    2.689576] pcieport 0003:00:00.0: enabling device (0000 -> 0002)
[    2.695672] pcieport 0003:00:00.0: enabling bus mastering
[    2.701417] mtk-pcie-gen3 11280000.pcie: msi#0x0 address_hi 0x0 address_lo 0x11280c00 data 0
[    2.709849] mtk-pcie-gen3 11280000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11280c00 data 1
[    2.718281] mtk-pcie-gen3 11280000.pcie: msi#0x2 address_hi 0x0 address_lo 0x11280c00 data 2
[    2.726709] mtk-pcie-gen3 11280000.pcie: msi#0x3 address_hi 0x0 address_lo 0x11280c00 data 3
[    2.735136] mtk-pcie-gen3 11280000.pcie: msi#0x4 address_hi 0x0 address_lo 0x11280c00 data 4
[    2.743564] mtk-pcie-gen3 11280000.pcie: msi#0x5 address_hi 0x0 address_lo 0x11280c00 data 5
[    2.751991] mtk-pcie-gen3 11280000.pcie: msi#0x6 address_hi 0x0 address_lo 0x11280c00 data 6
[    2.760416] mtk-pcie-gen3 11280000.pcie: msi#0x7 address_hi 0x0 address_lo 0x11280c00 data 7
[    2.768842] mtk-pcie-gen3 11280000.pcie: msi#0x8 address_hi 0x0 address_lo 0x11280c00 data 8
[    2.777269] mtk-pcie-gen3 11280000.pcie: msi#0x9 address_hi 0x0 address_lo 0x11280c00 data 9
[    2.785696] mtk-pcie-gen3 11280000.pcie: msi#0xa address_hi 0x0 address_lo 0x11280c00 data 10
[    2.794210] mtk-pcie-gen3 11280000.pcie: msi#0xb address_hi 0x0 address_lo 0x11280c00 data 11
[    2.802724] mtk-pcie-gen3 11280000.pcie: msi#0xc address_hi 0x0 address_lo 0x11280c00 data 12
[    2.811236] mtk-pcie-gen3 11280000.pcie: msi#0xd address_hi 0x0 address_lo 0x11280c00 data 13
[    2.819750] mtk-pcie-gen3 11280000.pcie: msi#0xe address_hi 0x0 address_lo 0x11280c00 data 14
[    2.828265] mtk-pcie-gen3 11280000.pcie: msi#0xf address_hi 0x0 address_lo 0x11280c00 data 15
[    2.836780] mtk-pcie-gen3 11280000.pcie: msi#0x10 address_hi 0x0 address_lo 0x11280c00 data 16
[    2.845380] mtk-pcie-gen3 11280000.pcie: msi#0x11 address_hi 0x0 address_lo 0x11280c00 data 17
[    2.853981] mtk-pcie-gen3 11280000.pcie: msi#0x12 address_hi 0x0 address_lo 0x11280c00 data 18
[    2.862582] mtk-pcie-gen3 11280000.pcie: msi#0x13 address_hi 0x0 address_lo 0x11280c00 data 19
[    2.871179] mtk-pcie-gen3 11280000.pcie: msi#0x14 address_hi 0x0 address_lo 0x11280c00 data 20
[    2.879780] mtk-pcie-gen3 11280000.pcie: msi#0x15 address_hi 0x0 address_lo 0x11280c00 data 21
[    2.888380] mtk-pcie-gen3 11280000.pcie: msi#0x16 address_hi 0x0 address_lo 0x11280c00 data 22
[    2.896981] mtk-pcie-gen3 11280000.pcie: msi#0x17 address_hi 0x0 address_lo 0x11280c00 data 23
[    2.905582] mtk-pcie-gen3 11280000.pcie: msi#0x18 address_hi 0x0 address_lo 0x11280c00 data 24
[    2.914181] mtk-pcie-gen3 11280000.pcie: msi#0x19 address_hi 0x0 address_lo 0x11280c00 data 25
[    2.922781] mtk-pcie-gen3 11280000.pcie: msi#0x1a address_hi 0x0 address_lo 0x11280c00 data 26
[    2.931381] mtk-pcie-gen3 11280000.pcie: msi#0x1b address_hi 0x0 address_lo 0x11280c00 data 27
[    2.939978] mtk-pcie-gen3 11280000.pcie: msi#0x1c address_hi 0x0 address_lo 0x11280c00 data 28
[    2.948580] mtk-pcie-gen3 11280000.pcie: msi#0x1d address_hi 0x0 address_lo 0x11280c00 data 29
[    2.957181] mtk-pcie-gen3 11280000.pcie: msi#0x1e address_hi 0x0 address_lo 0x11280c00 data 30
[    2.965781] mtk-pcie-gen3 11280000.pcie: msi#0x1f address_hi 0x0 address_lo 0x11280c00 data 31
[    2.974769] mtk-pcie-gen3 11280000.pcie: msi#0x0 address_hi 0x0 address_lo 0x11280c00 data 0
[    2.983266] pcieport 0003:00:00.0: PME: Signaling with IRQ 115
[    2.989195] pcieport 0003:00:00.0: AER: enabled with IRQ 115
[    2.994899] pcieport 0003:00:00.0: save config 0x00: 0x798814c3
[    3.000810] pcieport 0003:00:00.0: save config 0x04: 0x00100406
[    3.006722] pcieport 0003:00:00.0: save config 0x08: 0x06040001
[    3.012636] pcieport 0003:00:00.0: save config 0x0c: 0x00010000
[    3.018544] pcieport 0003:00:00.0: save config 0x10: 0x20200004
[    3.024455] pcieport 0003:00:00.0: save config 0x14: 0x00000000
[    3.030363] pcieport 0003:00:00.0: save config 0x18: 0x00010100
[    3.036276] pcieport 0003:00:00.0: save config 0x1c: 0x000001f1
[    3.042190] pcieport 0003:00:00.0: save config 0x20: 0x20f02080
[    3.048097] pcieport 0003:00:00.0: save config 0x24: 0x21b12101
[    3.054008] pcieport 0003:00:00.0: save config 0x28: 0x00000000
[    3.059916] pcieport 0003:00:00.0: save config 0x2c: 0x00000000
[    3.065827] pcieport 0003:00:00.0: save config 0x30: 0x00000000
[    3.071736] pcieport 0003:00:00.0: save config 0x34: 0x00000080
[    3.077644] pcieport 0003:00:00.0: save config 0x38: 0x00000000
[    3.083554] pcieport 0003:00:00.0: save config 0x3c: 0x00020172
[    3.177435] mtk-pcie-gen3 11290000.pcie: host bridge /soc/pcie@11290000 ranges:
[    3.184744] mtk-pcie-gen3 11290000.pcie: Parsing ranges property...
[    3.191010] mtk-pcie-gen3 11290000.pcie:       IO 0x0028000000..0x00281fffff -> 0x0028000000
[    3.199445] mtk-pcie-gen3 11290000.pcie:      MEM 0x0028200000..0x002fffffff -> 0x0028200000
[    3.443974] mtk-pcie-gen3 11290000.pcie: set IO trans window[0]: cpu_addr = 0x28000000, pci_addr = 0x28000000, size = 0x200000
[    3.455360] mtk-pcie-gen3 11290000.pcie: set MEM trans window[1]: cpu_addr = 0x28200000, pci_addr = 0x28200000, size = 0x200000
[    3.466825] mtk-pcie-gen3 11290000.pcie: set MEM trans window[2]: cpu_addr = 0x28400000, pci_addr = 0x28400000, size = 0x400000
[    3.478291] mtk-pcie-gen3 11290000.pcie: set MEM trans window[3]: cpu_addr = 0x28800000, pci_addr = 0x28800000, size = 0x800000
[    3.489756] mtk-pcie-gen3 11290000.pcie: set MEM trans window[4]: cpu_addr = 0x29000000, pci_addr = 0x29000000, size = 0x1000000
[    3.501305] mtk-pcie-gen3 11290000.pcie: set MEM trans window[5]: cpu_addr = 0x2a000000, pci_addr = 0x2a000000, size = 0x2000000
[    3.512856] mtk-pcie-gen3 11290000.pcie: set MEM trans window[6]: cpu_addr = 0x2c000000, pci_addr = 0x2c000000, size = 0x4000000
[    3.524532] mtk-pcie-gen3 11290000.pcie: PCI host bridge to bus 0002:00
[    3.557327] pci 0002:00:00.0: [14c3:7988] type 01 class 0x060400 PCIe Root Port
[    3.637742] pci 0002:01:00.0: [144d:a80a] type 00 class 0x010802 PCIe Endpoint
[    3.651618] pci 0002:01:00.0: 7.876 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x1 link at 0002:00:00.0 (capable of 63.012 Gb/s with 16.0 GT/s PCIe x4 link)
[    3.865697] pcieport 0002:00:00.0: assign IRQ: got 117
[    3.870828] pcieport 0002:00:00.0: enabling device (0000 -> 0002)
[    3.876923] pcieport 0002:00:00.0: enabling bus mastering
[    3.882667] mtk-pcie-gen3 11290000.pcie: msi#0x0 address_hi 0x0 address_lo 0x11290c00 data 0
[    3.891099] mtk-pcie-gen3 11290000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11290c00 data 1
[    3.899530] mtk-pcie-gen3 11290000.pcie: msi#0x2 address_hi 0x0 address_lo 0x11290c00 data 2
[    3.907958] mtk-pcie-gen3 11290000.pcie: msi#0x3 address_hi 0x0 address_lo 0x11290c00 data 3
[    3.916386] mtk-pcie-gen3 11290000.pcie: msi#0x4 address_hi 0x0 address_lo 0x11290c00 data 4
[    3.924816] mtk-pcie-gen3 11290000.pcie: msi#0x5 address_hi 0x0 address_lo 0x11290c00 data 5
[    3.933244] mtk-pcie-gen3 11290000.pcie: msi#0x6 address_hi 0x0 address_lo 0x11290c00 data 6
[    3.941670] mtk-pcie-gen3 11290000.pcie: msi#0x7 address_hi 0x0 address_lo 0x11290c00 data 7
[    3.950094] mtk-pcie-gen3 11290000.pcie: msi#0x8 address_hi 0x0 address_lo 0x11290c00 data 8
[    3.958521] mtk-pcie-gen3 11290000.pcie: msi#0x9 address_hi 0x0 address_lo 0x11290c00 data 9
[    3.966948] mtk-pcie-gen3 11290000.pcie: msi#0xa address_hi 0x0 address_lo 0x11290c00 data 10
[    3.975463] mtk-pcie-gen3 11290000.pcie: msi#0xb address_hi 0x0 address_lo 0x11290c00 data 11
[    3.983976] mtk-pcie-gen3 11290000.pcie: msi#0xc address_hi 0x0 address_lo 0x11290c00 data 12
[    3.992495] mtk-pcie-gen3 11290000.pcie: msi#0xd address_hi 0x0 address_lo 0x11290c00 data 13
[    4.001006] mtk-pcie-gen3 11290000.pcie: msi#0xe address_hi 0x0 address_lo 0x11290c00 data 14
[    4.009521] mtk-pcie-gen3 11290000.pcie: msi#0xf address_hi 0x0 address_lo 0x11290c00 data 15
[    4.018035] mtk-pcie-gen3 11290000.pcie: msi#0x10 address_hi 0x0 address_lo 0x11290c00 data 16
[    4.026636] mtk-pcie-gen3 11290000.pcie: msi#0x11 address_hi 0x0 address_lo 0x11290c00 data 17
[    4.035236] mtk-pcie-gen3 11290000.pcie: msi#0x12 address_hi 0x0 address_lo 0x11290c00 data 18
[    4.043840] mtk-pcie-gen3 11290000.pcie: msi#0x13 address_hi 0x0 address_lo 0x11290c00 data 19
[    4.052441] mtk-pcie-gen3 11290000.pcie: msi#0x14 address_hi 0x0 address_lo 0x11290c00 data 20
[    4.061038] mtk-pcie-gen3 11290000.pcie: msi#0x15 address_hi 0x0 address_lo 0x11290c00 data 21
[    4.069638] mtk-pcie-gen3 11290000.pcie: msi#0x16 address_hi 0x0 address_lo 0x11290c00 data 22
[    4.078239] mtk-pcie-gen3 11290000.pcie: msi#0x17 address_hi 0x0 address_lo 0x11290c00 data 23
[    4.086839] mtk-pcie-gen3 11290000.pcie: msi#0x18 address_hi 0x0 address_lo 0x11290c00 data 24
[    4.095439] mtk-pcie-gen3 11290000.pcie: msi#0x19 address_hi 0x0 address_lo 0x11290c00 data 25
[    4.104039] mtk-pcie-gen3 11290000.pcie: msi#0x1a address_hi 0x0 address_lo 0x11290c00 data 26
[    4.112640] mtk-pcie-gen3 11290000.pcie: msi#0x1b address_hi 0x0 address_lo 0x11290c00 data 27
[    4.121238] mtk-pcie-gen3 11290000.pcie: msi#0x1c address_hi 0x0 address_lo 0x11290c00 data 28
[    4.129838] mtk-pcie-gen3 11290000.pcie: msi#0x1d address_hi 0x0 address_lo 0x11290c00 data 29
[    4.138438] mtk-pcie-gen3 11290000.pcie: msi#0x1e address_hi 0x0 address_lo 0x11290c00 data 30
[    4.147039] mtk-pcie-gen3 11290000.pcie: msi#0x1f address_hi 0x0 address_lo 0x11290c00 data 31
[    4.156040] mtk-pcie-gen3 11290000.pcie: msi#0x0 address_hi 0x0 address_lo 0x11290c00 data 0
[    4.164541] pcieport 0002:00:00.0: PME: Signaling with IRQ 118
[    4.170469] pcieport 0002:00:00.0: AER: enabled with IRQ 118
[    4.176177] pcieport 0002:00:00.0: save config 0x00: 0x798814c3
[    4.182091] pcieport 0002:00:00.0: save config 0x04: 0x00100406
[    4.187999] pcieport 0002:00:00.0: save config 0x08: 0x06040001
[    4.193911] pcieport 0002:00:00.0: save config 0x0c: 0x00010000
[    4.199819] pcieport 0002:00:00.0: save config 0x10: 0x28300004
[    4.205731] pcieport 0002:00:00.0: save config 0x14: 0x00000000
[    4.211641] pcieport 0002:00:00.0: save config 0x18: 0x00010100
[    4.217549] pcieport 0002:00:00.0: save config 0x1c: 0x000001f1
[    4.223461] pcieport 0002:00:00.0: save config 0x20: 0x28202820
[    4.229369] pcieport 0002:00:00.0: save config 0x24: 0x0001fff1
[    4.235279] pcieport 0002:00:00.0: save config 0x28: 0x00000000
[    4.241187] pcieport 0002:00:00.0: save config 0x2c: 0x00000000
[    4.247097] pcieport 0002:00:00.0: save config 0x30: 0x00000000
[    4.253007] pcieport 0002:00:00.0: save config 0x34: 0x00000080
[    4.258914] pcieport 0002:00:00.0: save config 0x38: 0x00000000
[    4.264828] pcieport 0002:00:00.0: save config 0x3c: 0x00020175
[    4.358689] mtk-pcie-gen3 11300000.pcie: host bridge /soc/pcie@11300000 ranges:
[    4.365999] mtk-pcie-gen3 11300000.pcie: Parsing ranges property...
[    4.372270] mtk-pcie-gen3 11300000.pcie:       IO 0x0030000000..0x00301fffff -> 0x0030000000
[    4.380702] mtk-pcie-gen3 11300000.pcie:      MEM 0x0030200000..0x0037ffffff -> 0x0030200000
[    4.603932] mtk-pcie-gen3 11300000.pcie: set IO trans window[0]: cpu_addr = 0x30000000, pci_addr = 0x30000000, size = 0x200000
[    4.615318] mtk-pcie-gen3 11300000.pcie: set MEM trans window[1]: cpu_addr = 0x30200000, pci_addr = 0x30200000, size = 0x200000
[    4.626783] mtk-pcie-gen3 11300000.pcie: set MEM trans window[2]: cpu_addr = 0x30400000, pci_addr = 0x30400000, size = 0x400000
[    4.638248] mtk-pcie-gen3 11300000.pcie: set MEM trans window[3]: cpu_addr = 0x30800000, pci_addr = 0x30800000, size = 0x800000
[    4.649712] mtk-pcie-gen3 11300000.pcie: set MEM trans window[4]: cpu_addr = 0x31000000, pci_addr = 0x31000000, size = 0x1000000
[    4.661262] mtk-pcie-gen3 11300000.pcie: set MEM trans window[5]: cpu_addr = 0x32000000, pci_addr = 0x32000000, size = 0x2000000
[    4.672813] mtk-pcie-gen3 11300000.pcie: set MEM trans window[6]: cpu_addr = 0x34000000, pci_addr = 0x34000000, size = 0x4000000
[    4.684478] mtk-pcie-gen3 11300000.pcie: PCI host bridge to bus 0000:00
[    4.717270] pci 0000:00:00.0: [14c3:7988] type 01 class 0x060400 PCIe Root Port
[    4.797666] pci 0000:01:00.0: [14c3:7925] type 00 class 0x028000 PCIe Endpoint
[    5.033034] pcieport 0000:00:00.0: assign IRQ: got 120
[    5.038165] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
[    5.044261] pcieport 0000:00:00.0: enabling bus mastering
[    5.049983] mtk-pcie-gen3 11300000.pcie: msi#0x0 address_hi 0x0 address_lo 0x11300c00 data 0
[    5.058423] mtk-pcie-gen3 11300000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11300c00 data 1
[    5.066852] mtk-pcie-gen3 11300000.pcie: msi#0x2 address_hi 0x0 address_lo 0x11300c00 data 2
[    5.075280] mtk-pcie-gen3 11300000.pcie: msi#0x3 address_hi 0x0 address_lo 0x11300c00 data 3
[    5.083710] mtk-pcie-gen3 11300000.pcie: msi#0x4 address_hi 0x0 address_lo 0x11300c00 data 4
[    5.092139] mtk-pcie-gen3 11300000.pcie: msi#0x5 address_hi 0x0 address_lo 0x11300c00 data 5
[    5.100564] mtk-pcie-gen3 11300000.pcie: msi#0x6 address_hi 0x0 address_lo 0x11300c00 data 6
[    5.108992] mtk-pcie-gen3 11300000.pcie: msi#0x7 address_hi 0x0 address_lo 0x11300c00 data 7
[    5.117419] mtk-pcie-gen3 11300000.pcie: msi#0x8 address_hi 0x0 address_lo 0x11300c00 data 8
[    5.125850] mtk-pcie-gen3 11300000.pcie: msi#0x9 address_hi 0x0 address_lo 0x11300c00 data 9
[    5.134276] mtk-pcie-gen3 11300000.pcie: msi#0xa address_hi 0x0 address_lo 0x11300c00 data 10
[    5.142792] mtk-pcie-gen3 11300000.pcie: msi#0xb address_hi 0x0 address_lo 0x11300c00 data 11
[    5.151306] mtk-pcie-gen3 11300000.pcie: msi#0xc address_hi 0x0 address_lo 0x11300c00 data 12
[    5.159817] mtk-pcie-gen3 11300000.pcie: msi#0xd address_hi 0x0 address_lo 0x11300c00 data 13
[    5.168332] mtk-pcie-gen3 11300000.pcie: msi#0xe address_hi 0x0 address_lo 0x11300c00 data 14
[    5.176846] mtk-pcie-gen3 11300000.pcie: msi#0xf address_hi 0x0 address_lo 0x11300c00 data 15
[    5.185360] mtk-pcie-gen3 11300000.pcie: msi#0x10 address_hi 0x0 address_lo 0x11300c00 data 16
[    5.193961] mtk-pcie-gen3 11300000.pcie: msi#0x11 address_hi 0x0 address_lo 0x11300c00 data 17
[    5.202563] mtk-pcie-gen3 11300000.pcie: msi#0x12 address_hi 0x0 address_lo 0x11300c00 data 18
[    5.211161] mtk-pcie-gen3 11300000.pcie: msi#0x13 address_hi 0x0 address_lo 0x11300c00 data 19
[    5.219762] mtk-pcie-gen3 11300000.pcie: msi#0x14 address_hi 0x0 address_lo 0x11300c00 data 20
[    5.228362] mtk-pcie-gen3 11300000.pcie: msi#0x15 address_hi 0x0 address_lo 0x11300c00 data 21
[    5.236962] mtk-pcie-gen3 11300000.pcie: msi#0x16 address_hi 0x0 address_lo 0x11300c00 data 22
[    5.245562] mtk-pcie-gen3 11300000.pcie: msi#0x17 address_hi 0x0 address_lo 0x11300c00 data 23
[    5.254163] mtk-pcie-gen3 11300000.pcie: msi#0x18 address_hi 0x0 address_lo 0x11300c00 data 24
[    5.262763] mtk-pcie-gen3 11300000.pcie: msi#0x19 address_hi 0x0 address_lo 0x11300c00 data 25
[    5.271369] mtk-pcie-gen3 11300000.pcie: msi#0x1a address_hi 0x0 address_lo 0x11300c00 data 26
[    5.279967] mtk-pcie-gen3 11300000.pcie: msi#0x1b address_hi 0x0 address_lo 0x11300c00 data 27
[    5.288569] mtk-pcie-gen3 11300000.pcie: msi#0x1c address_hi 0x0 address_lo 0x11300c00 data 28
[    5.297168] mtk-pcie-gen3 11300000.pcie: msi#0x1d address_hi 0x0 address_lo 0x11300c00 data 29
[    5.305769] mtk-pcie-gen3 11300000.pcie: msi#0x1e address_hi 0x0 address_lo 0x11300c00 data 30
[    5.314370] mtk-pcie-gen3 11300000.pcie: msi#0x1f address_hi 0x0 address_lo 0x11300c00 data 31
[    5.323355] mtk-pcie-gen3 11300000.pcie: msi#0x0 address_hi 0x0 address_lo 0x11300c00 data 0
[    5.331855] pcieport 0000:00:00.0: PME: Signaling with IRQ 121
[    5.337789] pcieport 0000:00:00.0: AER: enabled with IRQ 121
[    5.343487] pcieport 0000:00:00.0: save config 0x00: 0x798814c3
[    5.349397] pcieport 0000:00:00.0: save config 0x04: 0x00100406
[    5.355310] pcieport 0000:00:00.0: save config 0x08: 0x06040001
[    5.361218] pcieport 0000:00:00.0: save config 0x0c: 0x00010000
[    5.367129] pcieport 0000:00:00.0: save config 0x10: 0x30500004
[    5.373041] pcieport 0000:00:00.0: save config 0x14: 0x00000000
[    5.378948] pcieport 0000:00:00.0: save config 0x18: 0x00010100
[    5.384859] pcieport 0000:00:00.0: save config 0x1c: 0x000001f1
[    5.390768] pcieport 0000:00:00.0: save config 0x20: 0x30403020
[    5.396682] pcieport 0000:00:00.0: save config 0x24: 0x0001fff1
[    5.402593] pcieport 0000:00:00.0: save config 0x28: 0x00000000
[    5.408501] pcieport 0000:00:00.0: save config 0x2c: 0x00000000
[    5.414412] pcieport 0000:00:00.0: save config 0x30: 0x00000000
[    5.420319] pcieport 0000:00:00.0: save config 0x34: 0x00000080
[    5.426229] pcieport 0000:00:00.0: save config 0x38: 0x00000000
[    5.432140] pcieport 0000:00:00.0: save config 0x3c: 0x00020178
[    5.526011] mtk-pcie-gen3 11310000.pcie: host bridge /soc/pcie@11310000 ranges:
[    5.533320] mtk-pcie-gen3 11310000.pcie: Parsing ranges property...
[    5.539586] mtk-pcie-gen3 11310000.pcie:       IO 0x0038000000..0x00381fffff -> 0x0038000000
[    5.548021] mtk-pcie-gen3 11310000.pcie:      MEM 0x0038200000..0x003fffffff -> 0x0038200000
[    5.786373] mtk-pcie-gen3 11310000.pcie: set IO trans window[0]: cpu_addr = 0x38000000, pci_addr = 0x38000000, size = 0x200000
[    5.797755] mtk-pcie-gen3 11310000.pcie: set MEM trans window[1]: cpu_addr = 0x38200000, pci_addr = 0x38200000, size = 0x200000
[    5.809221] mtk-pcie-gen3 11310000.pcie: set MEM trans window[2]: cpu_addr = 0x38400000, pci_addr = 0x38400000, size = 0x400000
[    5.820686] mtk-pcie-gen3 11310000.pcie: set MEM trans window[3]: cpu_addr = 0x38800000, pci_addr = 0x38800000, size = 0x800000
[    5.832150] mtk-pcie-gen3 11310000.pcie: set MEM trans window[4]: cpu_addr = 0x39000000, pci_addr = 0x39000000, size = 0x1000000
[    5.843699] mtk-pcie-gen3 11310000.pcie: set MEM trans window[5]: cpu_addr = 0x3a000000, pci_addr = 0x3a000000, size = 0x2000000
[    5.855249] mtk-pcie-gen3 11310000.pcie: set MEM trans window[6]: cpu_addr = 0x3c000000, pci_addr = 0x3c000000, size = 0x4000000
[    5.866913] mtk-pcie-gen3 11310000.pcie: PCI host bridge to bus 0001:00
[    5.899706] pci 0001:00:00.0: [14c3:7988] type 01 class 0x060400 PCIe Root Port
[    5.980091] pci 0001:01:00.0: [14c3:7906] type 00 class 0x028000 PCIe Endpoint
[    6.017946] pci 0001:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x1 link at 0001:00:00.0 (capable of 8.000 Gb/s with 5.0 GT/s PCIe x2 link)
[    6.274611] pcieport 0001:00:00.0: assign IRQ: got 123
[    6.279742] pcieport 0001:00:00.0: enabling device (0000 -> 0002)
[    6.285839] pcieport 0001:00:00.0: enabling bus mastering
[    6.291579] mtk-pcie-gen3 11310000.pcie: msi#0x0 address_hi 0x0 address_lo 0x11310c00 data 0
[    6.300011] mtk-pcie-gen3 11310000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11310c00 data 1
[    6.308443] mtk-pcie-gen3 11310000.pcie: msi#0x2 address_hi 0x0 address_lo 0x11310c00 data 2
[    6.316879] mtk-pcie-gen3 11310000.pcie: msi#0x3 address_hi 0x0 address_lo 0x11310c00 data 3
[    6.325308] mtk-pcie-gen3 11310000.pcie: msi#0x4 address_hi 0x0 address_lo 0x11310c00 data 4
[    6.333735] mtk-pcie-gen3 11310000.pcie: msi#0x5 address_hi 0x0 address_lo 0x11310c00 data 5
[    6.342162] mtk-pcie-gen3 11310000.pcie: msi#0x6 address_hi 0x0 address_lo 0x11310c00 data 6
[    6.350587] mtk-pcie-gen3 11310000.pcie: msi#0x7 address_hi 0x0 address_lo 0x11310c00 data 7
[    6.359013] mtk-pcie-gen3 11310000.pcie: msi#0x8 address_hi 0x0 address_lo 0x11310c00 data 8
[    6.367440] mtk-pcie-gen3 11310000.pcie: msi#0x9 address_hi 0x0 address_lo 0x11310c00 data 9
[    6.375868] mtk-pcie-gen3 11310000.pcie: msi#0xa address_hi 0x0 address_lo 0x11310c00 data 10
[    6.384381] mtk-pcie-gen3 11310000.pcie: msi#0xb address_hi 0x0 address_lo 0x11310c00 data 11
[    6.392901] mtk-pcie-gen3 11310000.pcie: msi#0xc address_hi 0x0 address_lo 0x11310c00 data 12
[    6.401415] mtk-pcie-gen3 11310000.pcie: msi#0xd address_hi 0x0 address_lo 0x11310c00 data 13
[    6.409925] mtk-pcie-gen3 11310000.pcie: msi#0xe address_hi 0x0 address_lo 0x11310c00 data 14
[    6.418441] mtk-pcie-gen3 11310000.pcie: msi#0xf address_hi 0x0 address_lo 0x11310c00 data 15
[    6.426955] mtk-pcie-gen3 11310000.pcie: msi#0x10 address_hi 0x0 address_lo 0x11310c00 data 16
[    6.435556] mtk-pcie-gen3 11310000.pcie: msi#0x11 address_hi 0x0 address_lo 0x11310c00 data 17
[    6.444156] mtk-pcie-gen3 11310000.pcie: msi#0x12 address_hi 0x0 address_lo 0x11310c00 data 18
[    6.452756] mtk-pcie-gen3 11310000.pcie: msi#0x13 address_hi 0x0 address_lo 0x11310c00 data 19
[    6.461356] mtk-pcie-gen3 11310000.pcie: msi#0x14 address_hi 0x0 address_lo 0x11310c00 data 20
[    6.469953] mtk-pcie-gen3 11310000.pcie: msi#0x15 address_hi 0x0 address_lo 0x11310c00 data 21
[    6.478553] mtk-pcie-gen3 11310000.pcie: msi#0x16 address_hi 0x0 address_lo 0x11310c00 data 22
[    6.487154] mtk-pcie-gen3 11310000.pcie: msi#0x17 address_hi 0x0 address_lo 0x11310c00 data 23
[    6.495754] mtk-pcie-gen3 11310000.pcie: msi#0x18 address_hi 0x0 address_lo 0x11310c00 data 24
[    6.504355] mtk-pcie-gen3 11310000.pcie: msi#0x19 address_hi 0x0 address_lo 0x11310c00 data 25
[    6.512956] mtk-pcie-gen3 11310000.pcie: msi#0x1a address_hi 0x0 address_lo 0x11310c00 data 26
[    6.521556] mtk-pcie-gen3 11310000.pcie: msi#0x1b address_hi 0x0 address_lo 0x11310c00 data 27
[    6.530154] mtk-pcie-gen3 11310000.pcie: msi#0x1c address_hi 0x0 address_lo 0x11310c00 data 28
[    6.538755] mtk-pcie-gen3 11310000.pcie: msi#0x1d address_hi 0x0 address_lo 0x11310c00 data 29
[    6.547356] mtk-pcie-gen3 11310000.pcie: msi#0x1e address_hi 0x0 address_lo 0x11310c00 data 30
[    6.555956] mtk-pcie-gen3 11310000.pcie: msi#0x1f address_hi 0x0 address_lo 0x11310c00 data 31
[    6.564949] mtk-pcie-gen3 11310000.pcie: msi#0x0 address_hi 0x0 address_lo 0x11310c00 data 0
[    6.573453] pcieport 0001:00:00.0: PME: Signaling with IRQ 124
[    6.579382] pcieport 0001:00:00.0: AER: enabled with IRQ 124
[    6.585084] pcieport 0001:00:00.0: save config 0x00: 0x798814c3
[    6.590995] pcieport 0001:00:00.0: save config 0x04: 0x00100406
[    6.596910] pcieport 0001:00:00.0: save config 0x08: 0x06040001
[    6.602821] pcieport 0001:00:00.0: save config 0x0c: 0x00010000
[    6.608729] pcieport 0001:00:00.0: save config 0x10: 0x38500004
[    6.614640] pcieport 0001:00:00.0: save config 0x14: 0x00000000
[    6.620548] pcieport 0001:00:00.0: save config 0x18: 0x00010100
[    6.626459] pcieport 0001:00:00.0: save config 0x1c: 0x000001f1
[    6.632371] pcieport 0001:00:00.0: save config 0x20: 0x38203820
[    6.638280] pcieport 0001:00:00.0: save config 0x24: 0x38413831
[    6.644190] pcieport 0001:00:00.0: save config 0x28: 0x00000000
[    6.650097] pcieport 0001:00:00.0: save config 0x2c: 0x00000000
[    6.656007] pcieport 0001:00:00.0: save config 0x30: 0x00000000
[    6.661917] pcieport 0001:00:00.0: save config 0x34: 0x00000080
[    6.667824] pcieport 0001:00:00.0: save config 0x38: 0x00000000
[    6.673734] pcieport 0001:00:00.0: save config 0x3c: 0x0002017b
[    7.894352] mtk-pcie-gen3 11290000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11290c00 data 1
[    8.021122] mtk-pcie-gen3 11290000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11290c00 data 1
[    8.029577] mtk-pcie-gen3 11290000.pcie: msi#0x2 address_hi 0x0 address_lo 0x11290c00 data 2
[    8.038028] mtk-pcie-gen3 11290000.pcie: msi#0x3 address_hi 0x0 address_lo 0x11290c00 data 3
[    8.046477] mtk-pcie-gen3 11290000.pcie: msi#0x4 address_hi 0x0 address_lo 0x11290c00 data 4
[    8.054929] mtk-pcie-gen3 11290000.pcie: msi#0x5 address_hi 0x0 address_lo 0x11290c00 data 5
[   19.811343] mtk-pcie-gen3 11310000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11310c00 data 1
[   20.294797] resource: Unaddressable device pcie@11280000 [mem 0x20200000-0x27ffffff] conflicts with [mem 0x21800000-0x21807fff]
[   20.306307] resource: Unaddressable device pcie@11280000 [mem 0x20200000-0x27ffffff] conflicts with [mem 0x20800000-0x20ffffff]
[   20.327270] mtk-pcie-gen3 11280000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11280c00 data 1
[   20.335874] mtk-pcie-gen3 11280000.pcie: msi#0x2 address_hi 0x0 address_lo 0x11280c00 data 2
[   20.344377] mtk-pcie-gen3 11280000.pcie: msi#0x3 address_hi 0x0 address_lo 0x11280c00 data 3
[   20.352875] mtk-pcie-gen3 11280000.pcie: msi#0x4 address_hi 0x0 address_lo 0x11280c00 data 4
[   20.361364] mtk-pcie-gen3 11280000.pcie: msi#0x5 address_hi 0x0 address_lo 0x11280c00 data 5
[   20.369829] mtk-pcie-gen3 11280000.pcie: msi#0x6 address_hi 0x0 address_lo 0x11280c00 data 6
[   20.378320] mtk-pcie-gen3 11280000.pcie: msi#0x7 address_hi 0x0 address_lo 0x11280c00 data 7
[   20.386806] mtk-pcie-gen3 11280000.pcie: msi#0x8 address_hi 0x0 address_lo 0x11280c00 data 8
[   20.444673] mtk-pcie-gen3 11300000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11300c00 data 1

Probable solution?


DTS
pcie@11280000 {
    compatible = "mediatek,mt7988-pcie", "mediatek,mt8192-pcie";
    reg = <0 0x11280000 0 0x4000>;
    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
    
    reset-gpios = <&pio 74 GPIO_ACTIVE_LOW>;
    
    status = "okay";
};

ptf · August 2, 2026, 6:05pm

Does not work for me.

echo 1 > /sys/bus/pci/devices/0003:01:00.0/remove
echo 1 > /sys/bus/pci/rescan

Well, that does appear to remove and add back the modem but it does not seem to resolve the address conflict

root@OpenWrt:~# echo 1 > /sys/bus/pci/rescan
[  210.947294] pci_bus 0003:00: scanning bus
[  210.952371] pcieport 0003:00:00.0: scanning [bus 01-01] behind bridge, pass 0
[  210.959520] pci_bus 0003:01: scanning bus
[  210.963552] pci 0003:01:00.0: [14c3:4d75] type 00 class 0x0d4000 PCIe Endpoint
[  210.970796] pci 0003:01:00.0: BAR 0 [mem 0x21800000-0x21807fff 64bit pref]
[  210.977680] pci 0003:01:00.0: BAR 2 [mem 0x20800000-0x20ffffff 64bit]
[  210.984125] pci 0003:01:00.0: BAR 4 [mem 0x21000000-0x217fffff 64bit pref]
[  210.991108] pci 0003:01:00.0: supports D1 D2
[  210.995369] pci 0003:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[  211.001979] pci 0003:01:00.0: PME# disabled
[  211.006200] pci 0003:01:00.0: 7.876 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x1 link at 0003:00:00.0 (capable of 15.752 Gb/s with 8.0 GT/s PCIe x2 link)
[  211.021384] pci_bus 0003:01: bus scan returning with max=01
[  211.026957] pcieport 0003:00:00.0: scanning [bus 01-01] behind bridge, pass 1
[  211.034083] pci_bus 0003:00: bus scan returning with max=01
[  211.039660] pci 0003:01:00.0: BAR 2 [mem 0x20800000-0x20ffffff 64bit]: assigned
[  211.046972] pci 0003:01:00.0: BAR 4 [mem 0x21000000-0x217fffff 64bit pref]: assigned
[  211.054712] pci 0003:01:00.0: BAR 0 [mem 0x21800000-0x21807fff 64bit pref]: assigned
[  211.062478] pci 0003:01:00.0: save config 0x00: 0x4d7514c3
[  211.067960] pci 0003:01:00.0: save config 0x04: 0x00100002
[  211.073436] pci 0003:01:00.0: save config 0x08: 0x0d400001
[  211.078918] pci 0003:01:00.0: save config 0x0c: 0x00000000
[  211.084393] pci 0003:01:00.0: save config 0x10: 0x2180000c
[  211.089873] pci 0003:01:00.0: save config 0x14: 0x00000000
[  211.095347] pci 0003:01:00.0: save config 0x18: 0x20800004
[  211.100879] pci 0003:01:00.0: save config 0x1c: 0x00000000
[  211.106360] pci 0003:01:00.0: save config 0x20: 0x2100000c
[  211.111836] pci 0003:01:00.0: save config 0x24: 0x00000000
[  211.117315] pci 0003:01:00.0: save config 0x28: 0x00000000
[  211.122790] pci 0003:01:00.0: save config 0x2c: 0x35001cf8
[  211.128268] pci 0003:01:00.0: save config 0x30: 0x00000000
[  211.133743] pci 0003:01:00.0: save config 0x34: 0x00000080
[  211.139222] pci 0003:01:00.0: save config 0x38: 0x00000000
[  211.144696] pci 0003:01:00.0: save config 0x3c: 0x00000172
[  211.150282] mtk_t7xx 0003:01:00.0: assign IRQ: got 114
[  211.155429] mtk_t7xx 0003:01:00.0: enabling bus mastering
[  211.160827] resource: Unaddressable device pcie@11280000 [mem 0x20200000-0x27ffffff] conflicts with [mem 0x21800000-0x21807fff]
[  211.172308] resource: Unaddressable device pcie@11280000 [mem 0x20200000-0x27ffffff] conflicts with [mem 0x20800000-0x20ffffff]
[  211.185774] mtk-pcie-gen3 11280000.pcie: msi#0x1 address_hi 0x0 address_lo 0x11280c00 data 1
[  211.194238] mtk-pcie-gen3 11280000.pcie: msi#0x2 address_hi 0x0 address_lo 0x11280c00 data 2
[  211.202701] mtk-pcie-gen3 11280000.pcie: msi#0x3 address_hi 0x0 address_lo 0x11280c00 data 3
[  211.211150] mtk-pcie-gen3 11280000.pcie: msi#0x4 address_hi 0x0 address_lo 0x11280c00 data 4
[  211.219603] mtk-pcie-gen3 11280000.pcie: msi#0x5 address_hi 0x0 address_lo 0x11280c00 data 5
[  211.228051] mtk-pcie-gen3 11280000.pcie: msi#0x6 address_hi 0x0 address_lo 0x11280c00 data 6
[  211.236500] mtk-pcie-gen3 11280000.pcie: msi#0x7 address_hi 0x0 address_lo 0x11280c00 data 7
[  211.244941] mtk-pcie-gen3 11280000.pcie: msi#0x8 address_hi 0x0 address_lo 0x11280c00 data 8

By the way the schematic you posted for the M.2 card connected to SIM1 differs from the one I can download from the net - the general card reset line just has a cap to ground in the one I have to provide a power on reset.

svy · August 3, 2026, 4:15am

The log clearly shows that after the scan command:

The controller detected a PCIe Endpoint with vendor ID 14c3:4d75 this is precisely the Fibocom FM350-GL modem based on the MediaTek T700 chipset.
The mtk_t7xx driver picked up the device, assigned an interrupt IRQ 114, and enabled bus mastering.
Memory regions (BAR 0, BAR 2, BAR 4) were allocated, and MSI lines for the mtk-pcie-gen3 controller interrupts were initialized.

In this case, we are talking about PERST# 50 pin.