CPU cache on dts

I’ve noticed that l1 and l2 cache aren’t defined in the dts file, while it is defined for some other MediaTek SOCs. From my experience with embedded chips, the cache is simply hardware and you don’t define anything, but it’s good to know the sizes and addresses so you can invalidate the cache on certain situations and maybe do some sanity checks. So do we need to define it or not? What is it used for?

No one knows? @frank-w @dangowrt ?

No,i don’t remember such setting and imho there is access to such cache as it is for cpu only