Communication with multiple uart interface

Hello i have a BPI-R2 when i typed dmesg | grep tty i saw there is 4 serial interface calles ttyS0,ttyS1,ttyS2,ttyS3 i want to use all of them but i do not know how can i acces gpio pins of these interfaces. Could you help me ? Best regards I send request for schematic but i did not get any response now. If you have could you share with me

Schematics for R2 are public, find them here:

I think there are only 3 usable UARTs on the R2, and one of them is usually used as debugging console. The other two can be found on the 40-pin GPIO header:


Afair there was a 4th with only solder pads but i don’t remember where it was as it was not easy usable and i did not need 4 :stuck_out_tongue:

Afair the CTS/DTS signals of the debugging UART are pads next to the 3-pin header. According to pinctrl UART3 RX/TX is on pins 242, 243 which is shared with UART2 RTS/CTS which is the debugging UART. So by switching pinctrl to use those pins as UART you may gain a 4th UART on those pads.


Ah,right,wasn’t sure it were the pads near debug-uart,but this was already in my mind. That requires maybe a similar patch line we did on r3 for the uarts (splitting pins into rx/tx and cts/rts).

How can i use pinctrl , I am new at embedded linux. could you share a example document on banana pi ? Best regards

Can I change pin of ttyS3 to GPIO pin by software ?

Uart3 is already defined and if found by system it should work.

Uart2 has no own pinctrl defined there…maybe it uses some defaults in driver or inherits settings from uboot

Hello I want to move my project from BPI-R2 to BPI R2 PRO according to this page( there is 4 uart pins ? Is there any problem about using the four uart of bpi-r2 pro ? Best regards

You have uart 0,5,7 and 9 on gpio-header, for uart9 you have to disable spi3+pwm12+pwm13 in bpi-r2pro.dts

Btw. The official page states Debug-uart is uart0 (@sinovoip pls fix) ,but schematic (and my tests/dts) says uart2.

Note that bpi-r2-pro is completely different to bpi-r2. Different soc, different bootchain and uboot config, mainline uboot currently broken (2022-04 usable from my repo), wan=eth0,lan-ports=eth1, dsa driver mainline,but needs a patch to get ~1Gbit (not 2.5gbit like r2). Pcie not yet mainline

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