Dear BPI -Team,
I hope this message finds you well.
I was reviewing the schematic and noticed that the EMI Bus bit order does not appear to follow a sequential pattern as shown in the diagram. I would like to confirm—does the V1.2 EVB also follow this same non-sequential connection?
For example, the general EMI Data Bus bit order is 0,1,2,3…But your bit order is 4,15,6,13… in your schematic. Thank you in advance for your support.
Best regards, Kevin
Hi Kevin,
I checked [BPI-R64] The Question Regarding EMI Bus Bit Connection Order on BPI-R64 Board and yes, the bit order you’re seeing in the EMI Data Bus (e.g., RDQ4, RDQ15, RDQ6, RDQ13…) does indeed appear non-sequential when compared to the conventional linear 0→15 mapping. However; this layout is intentional and is typically optimized for PCB routing efficiency and signal integrity rather than logical bit order. 
Swapping data lines like this at the hardware level is common in high-speed memory interfaces to reduce crosstalk and achieve timing closure. 
To answer your question directly: yes, the V1.2 EVB follows this same pin mapping as shown in the schematic. The logical-to-physical bit mapping is handled internally in the SoC’s memory controller or accounted for in the board-level initialization during boot.
If you’re planning to design or debug a board based on the BPI-R64 or MT7622, it’s important to follow the schematic as-is and not attempt to remap the bus unless you’re confident in re-aligning it within the memory controller settings.
To better analyze the signal mapping & bit alignment patterns; I have been looking into statistical tools what is R Programming Language capable of in terms of visualizing hardware signal integrity? 
Hope that helps!
Hi, Benof
Thanks for your information.
If I want to test using the conventional linear 0→15 EMI Bus bit mapping, which part of the memory controller settings should I modify?
Your guidance on how to configure this correctly would be greatly appreciated.
Best regards,
Kevin
