BPI-R64 current u-boot support

with your Patch and the 2014-source i added the jumparch64 to preserve compatibility (64bit kernel in 32bit uImage) with upstream uboot-code

made a quick test…works so far (except ethernet of course)…it boots with bpi’s ATF and i can load 32bit uImage containing 64bit kernel

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Update. Here is version based on @sam33’s patches:

It support SD/MMC/NAND.

It also has an USB support, but it won’t works. Sees only root hub emulation.

Here is two issues:

  1. SPI NAND works much slower if you initialize SD before it. Seems wrong clock sharing or misuse.
  2. No real USB devices visible.

@sam33 can you please do quick look on it and point me what to do? In case of XHCI we have clock named CLK_SSUSB_MCU_EN. I saw similar MCU clock source somewhere else. Maybe we have to power up that MCU first?


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PCI Express finally works. But dunno yet, why is SATA SSD behind PCI AHCI card does not detect. Controller see link, but can’t read. Maybe power related.

good news: first Patchset is merged: https://patchwork.ozlabs.org/patch/1220976/

do we want to add separate dts for r64 (at least for memory-node 256M vs. 1G) and 32-bit config (to stay compatible with current kernels/images)?

ethernet-patch is posted: https://patchwork.ozlabs.org/cover/1226407/ :slight_smile:

on first test (build 32bit-version and load via tftp) i got this

Net:   error: unsupported switch
No ethernet found.

tried same with 64bit-repo, result is same… :frowning:

and it’s clear why this is shown:

I tried to use mainline u-boot https://github.com/u-boot/u-boot to boot from SD, it seems I should need ATF image. I get the ATF image from BPI-R64 current u-boot support

U-boot hangs at:

F0: 102B 0000                                                                   
F6: 3800 00A0                                                                   
F3: 4000 0036                                                                   
F5: 0000 0000                                                                   
V0: 0000 0000 [0001]                                                            
00: 0000 0000                                                                   
BP: 0000 0041 [0000]                                                            
G0: 0190 0000                                                                   
T0: 0000 04ED [000F]                                                            
Jump to BL                                                                      
UNIVPLL_CON0 = 0xFE000000!!!                                                    
mt_pll_init: Set pll frequency for 25M crystal                                  
[PMIC_WRAP]wrap_init pass,the return value=0.                                   
[pmic_init] Preloader Start..................                                   
[pmic_init] MT6380 CHIP Code, reg_val = 0, 1:E2  0:E3                           
[pmic_init] Done...................                                             
Chip part number:7622A                                                          
MT7622 Version: 1.2.7, (iPA)                                                    
SSC OFF                                                                         
mt_pll_post_init: mt_get_cpu_freq = 1350000Khz                                  
mt_pll_post_init: mt_get_mem_freq = 1600000Khz                                  
mt_pll_post_init: mt_get_bus_freq = 1119920Khz                                  
[PLFM] Init I2C: OK(0)                                                          
[BLDR] Build Time: 20181123-214255                                              
==== Dump RGU Reg ========                                                      
RGU MODE:     4D                                                                
RGU LENGTH:   FFE0                                                              
RGU STA:      0                                                                 
RGU INTERVAL: FFF                                                               
RGU SWSYSRST: 8000                                                              
==== Dump RGU Reg End ====                                                      
RGU: g_rgu_satus:0                                                              
 mtk_wdt_mode_config  mode value=10, tmp:22000010                               
PL P ON                                                                         
WDT does not trigger reboot                                                     
WDT NONRST=0x20000000                                                           
WDT IRQ_EN=0x340003                                                             
RGU mtk_wdt_init:MTK_WDT_DEBUG_CTL(590200F3)                                    
[EMI] MDL number = 2                                                            
[EMI] DRAMC calibration start                                                   
[EMI] DRAMC calibration end                                                     
[EMI]rank0 size: 0x40000000                                                     
[MEM] complex R/W mem test pass                                                 
RAM_CONSOLE wdt status (0x0)=0x0                                                
[mmc_init]: msdc1 start mmc_init_host() in PL...                                
[msdc_init]: msdc1 Host controller intialization start                          
[SD1] Pins mode(1), none(0), down(1), up(2), keep(3)                            
[SD1] Pins mode(2), none(0), down(1), up(2), keep(3)                            
[info][msdc_config_clksrc] input clock is 200000kHz                             
[SD1] Bus Width: 1                                                              
[info][msdc_config_clksrc] input clock is 200000kHz                             
[SD1] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(193) DS(0) RS(0)         
[msdc_init]: msdc1 Host controller intialization done                           
[mmc_init]: msdc1 start mmc_init_card() in PL...                                
[mmc_init_card]: start                                                          
[SD1] Bus Width: 4                                                              
[SD1] Size: 29664 MB, Max.Speed: 25000 kHz, blklen(512), nblks(60751872), ro(0) 
[mmc_init_mem_card 3140][SD1] Initialized, SD10                                 
before host->cur_bus_clk(259067)                                                
[info][msdc_config_clksrc] input clock is 200000kHz                             
[SD1] SET_CLK(25000kHz): SCLK(25000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0)       
[mmc_init_card]: finish successfully                                            
[PLFM] Init Boot Device: OK(0)                                                  
[GPT_PL](BPI)Parsing Primary GPT now...                                         
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)     
[GPT_PL]Success to find valid GPT.                                              
[PART] blksz: 512B                                                              
[PART] [0x0000000000020000-0x000000000007FFFF] "preloader" (768 blocks)         
[PART] [0x0000000000080000-0x00000000000BFFFF] "tee1" (512 blocks)              
[PART] [0x00000000000C0000-0x000000000013FFFF] "lk" (1024 blocks)               
Device APC domain init setup:                                                   
Domain Setup (0x0)                                                              
Domain Setup (0x0)                                                              
Device APC domain after setup:                                                  
Domain Setup (0x0)                                                              
Domain Setup (0x0)                                                              
[get_part] part->nr_sects=768, part->info->name=preloader                       
[get_part] part->nr_sects=512, part->info->name=tee1                            
[get_part] part->nr_sects=1024, part->info->name=lk                             
[PART] Image with part header                                                   
[PART] name : U-Boot                                                            
[PART] addr : 41E00000h mode : -1                                               
[PART] size : 462615                                                            
[PART] magic: 58881688h                                                         
[PART] load "lk" from 0x00000000000C0200 (dev) to 0x41E00000 (mem) [SUCCESS]    
[PART] load speed: 3529KB/s, 462615 bytes, 128ms                                
load lk (ret=0)                                                                 
[get_part] part->nr_sects=768, part->info->name=preloader                       
[get_part] part->nr_sects=512, part->info->name=tee1                            
[PART] Image with part header                                                   
[PART] name : atf                                                               
[PART] addr : FFFFFFFFh mode : -1                                               
[PART] size : 62032                                                             
[PART] magic: 58881688h                                                         
[PART] load "tee1" from 0x0000000000080200 (dev) to 0x43000DC0 (mem) [SUCCESS]  
[PART] load speed: 2883KB/s, 62032 bytes, 21ms                                  
load tee1 (ret=0)                                                               
[BLDR] bldr load tee part ret=0x0, addr=0x43001000                              
[get_part] part->nr_sects=768, part->info->name=preloader                       
[get_part] part->nr_sects=512, part->info->name=tee1                            
[get_part] part->nr_sects=1024, part->info->name=lk                             
[BLDR] boot part. not found                                                     
[BLDR] part_load_images ret=0x0                                                 
[BLDR] Others, jump to ATF                                                      
[BLDR] jump to 0x41E00000                                                       
[BLDR] <0x41E00000>=0x1400000A                                                  
[BLDR] <0x41E00004>=0xD503201F                                                  
U-Boot 2020.01-00755-gad647690b1 (Jan 22 2020 - 10:21:08 +0300)                 
CPU:   MediaTek MT7622                                                          
Model: mt7622-rfb                                                               
DRAM:  256 MiB                                                                  
initcall sequence 000000004ffd30d0 failed at call 0000000041e0cd34 (err=-22)    
### ERROR ### Please RESET the board ###                                        

Any idea? Thanks.

Please try to not set CONFIG_BINMAN_FDT in u-boot .config.
It seem that recent commit caused this problem

Works for me, thanks!

This option seems new…maybe this is the commit which breaks boot…looks like it is not part of 2020-01 and merged later


the return log_msg_ret() causing an exit from chain so the further entries are not executed

38 int binman_init(void)
39 {
40         binman = malloc(sizeof(struct binman_info));
41         printf("%s:%d",__FUNCTION__,__LINE__);
42         if (!binman)
43                 return log_msg_ret("space for binman", -ENOMEM);
44         printf("%s:%d",__FUNCTION__,__LINE__);
45         binman->image = ofnode_path("/binman");
46         printf("%s:%d",__FUNCTION__,__LINE__);
47         if (!ofnode_valid(binman->image))
48                 return log_msg_ret("binman node", -EINVAL);
50         printf("%s:%d",__FUNCTION__,__LINE__);
51         return 0;
52 }

results in this:

binman_init:41binman_init:44binman_init:46initcall sequence 000000004ffd2588 failed at call 0000000041e0cdec (err=-22)

so this line seems to break:

return log_msg_ret("binman node", -EINVAL); //-EINVAL=-22

the binman_init is added to init_sequence_r[] which is executed by initcall_run_list

./common/board_r.c:897:	if (initcall_run_list(init_sequence_r))


40                 ret = (*init_fnc_ptr)();
41                 if (ret) {
42                         printf("initcall sequence %p failed at call %p (err=%d)\n", //<<<<<<<<< show error and then exit init-list execution on error 
43                                init_sequence,
44                                (char *)*init_fnc_ptr - reloc_ofs, ret);
45                         return -1;
46                 }

posted bug to author and mailinglist…

Out of curiosity, how did you build u-boot with ATF? Do you have plans to submit the patch to mainline?


imho he does not build uboot with atf…atf is flashed separately to storage.

If you want to stay on bpi atf (to load 64bit kernel in 32bit container) you can try rays patch-config to build 32bit uboot. You find it also on my repo…

i uploaded 2020-04-rc1 with changes for r2/r64 (change board in build.conf) to my uboot-repo (branch 2020-04-bpi-all).

disabled binman_fdt due to the boot-error (have not got any response to bug-report yet)

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my fix for mtk-eth-driver (warnings if built for aarch64) and mt7622 ethernet-support-patches (without switch) are merged.

got response from simon regarding the binman-issue…i guess we need something like this:

but i do not know what are the right files for r64…maybe an empty binman-node is enough, cause breaking code only looks for binman-node, but not for its content

Edit february 16th: Good news: i’ve got uboot ethernet driver from landen chao and on my quick tests it is working well on r64 (and r2)

Btw. Also r2 is affected from binman-issue so i have disabled it there too

edit february 23: @sam33 posted a series adding pwm-support and fixing binman-issue

added this series to current state (including mt7531 driver) and reverting my changes to defconfig regarding binman

Example for blinking LED with PWM

1. We need a PWM driver in U-boot to control hardware.

submitted patch:

2. We need to enable PWM in dts and configure pinctrl

diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 05502bddec..165496e8d9 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -69,6 +69,13 @@

+       pwm_pins: pwm1 {
+               mux {
+                       function = "pwm";
+                       groups = "pwm_ch1_0" ;
+               };
+       };
        watchdog_pins: watchdog-default {
                mux {
                        function = "watchdog";
@@ -155,6 +162,12 @@
        status = "okay";

+&pwm {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pwm_pins>;
+       status = "okay";
 &mmc0 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc0_pins_default>;

In this example, we use bpir64 pin 11 (UART1-TXD/GPIO51/TXD2/PWM_CH1) as PWM channel 1 (pwm_id=0), and connect this pin to a LED.

3. We need an application to access u-boot PWM API as a u-boot command

pwm 0 config 1000000000 500000000    
pwm 0 enable    

LED on (0.5 seconds) --> LED off (0.5 seconds) --> LED on (0.5 seconds) --> …

diff --git a/cmd/pwm.c b/cmd/pwm.c
new file mode 100644
index 0000000000..efd2f4590d
--- /dev/null
+++ b/cmd/pwm.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2020 MediaTek Inc.
+ * 
+ * Author: Sam Shih <[email protected]>
+ */
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <pwm.h>
+#include <dm/uclass-internal.h>
+int do_pwm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+       struct udevice *dev;
+       unsigned long pwm_id, period, duty;
+       if (uclass_get_device(UCLASS_PWM, 0, &dev)) {
+               printf("unable to find pwm driver\n");
+               return CMD_RET_FAILURE;
+       }
+       if (argc < 2)
+               return CMD_RET_USAGE;
+       pwm_id = simple_strtoul(argv[1], NULL, 0);
+       if (strncmp(argv[2], "config", 10) == 0) {
+               if (argc < 4)
+                       return CMD_RET_USAGE;
+               period = simple_strtoul(argv[3], NULL, 0);
+               duty = simple_strtoul(argv[4], NULL, 0);
+               if (pwm_set_config(dev, pwm_id, period, duty)) {
+                       printf("unable to config pwm driver\n");
+                       return CMD_RET_FAILURE;
+               }
+       }
+       else if (strncmp(argv[2], "enable", 10) == 0) {
+               pwm_set_enable(dev, pwm_id, true);
+       }
+       else if (strncmp(argv[2], "disable", 10) == 0) {
+               pwm_set_enable(dev, pwm_id, false);
+       }
+       return 0;
+       pwm, 5, 1, do_pwm,
+       "manage PWMs\n",
+       "<pwm_id> [config|enable|disable]\n"
+       "config: <pwm_id> config <period_in_ns> <duty_in_ns>\n"
+       "enable: <pwm_id> enable\n"
+       "disable: <pwm_id> disable\n"
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After i changed the right dts pwm is working (~1s blinking), using pins 9 (gnd)+11 (pwm)

maybe you can help adding the other pwm in linux dts?

Hi Sam, Would you please provide a ATF file just for 64bit u-boot, regardless of whether the WPS key is pressed or not? Thank you a lot !

why do you need this? sams ATF is capable for booting 64bit uboot without WPS-button press, so you can boot 64bit uboot…

i only need the reverse way (default 32 with jumparch64,wps => 64), @sam33 can you post it to me? so i’m able to test 64bit-mode too and do not break current 32bit-uboot-behaviour

I am debugging another custom board of mt7622. The WPS button on this board has other uses. The initial value on this pin is not sure.

Hi Frank, I got ATF file which you want from MTK, please try it.mt7622_atf_push_wps_uboot_64.img (61.1 KB)



thank you for the ATF

made a quick test…boots 32bit-uboot like the BPI-ATF and contains the jumparch64-target to load 64bit kernel from 32bit uImage (build by mkimage -a armhf). also tried booting with WPS-Button (left from Ethernet-Ports) and it does not load 32bit uboot…like i expected…need to find some time to flash 64bit uboot (have not much time currently because of SARS-CoV2 Limitations - 2 kids at home).