BPI-R64 current u-boot support

frank-w · November 6, 2019, 7:23am

hi, it does not contain any code for r64…

it would be nice to start repo with upstream u-boot and add your Patches on top (not one commit including upstream-source mixed with your changes), so everybody can see what is changed…

as an example i’ve added content of this folder to a branch in my repo:

https://github.com/frank-w/u-boot/commits/2019-07-bpi

but good that are no objects and generated files in the folder uploaded

ray · November 6, 2019, 7:52am

@sinovoip Many thanks!

Why don’t you push it as fork of mainline uboot?

sam33 · November 6, 2019, 3:22pm

Update our latest status for developing mt7622 upstream uboot
We have some major differences with Ray’s version

We use 64-bit u-boot because it is reasonable for 7622 which is ARMv8 architecture
We focus on Nand/Nor flash first, due to we use RFBs which are SPI-nand/SPI-nor
We will try Ray’s eMMC/SD patches to test eMMC and SD directly in BPIR64.

Status:

Serial - done
Timer - done
SD - not started
eMMC - ongoing
SNFI - done (for nand/nor)
Ethernet - ongoing
Switch - ongoing
PCI-E - todo
USB - todo
Clock - done (also fix some bugs in mtk-clk.c)
Pinctrl - done
Watchdog - ongoing
Reset - ongoing

It seems that some works are overlapping (with Ray’s works), maybe we can integrate the patches of both sides, but we think mt7622 upstrem u-boot should be 64 bits.

frank-w · November 6, 2019, 3:31pm

Can we see your current work to compare / migrate to 64bit too?

ray · November 8, 2019, 3:03pm

@Ryder.Lee @moore @sam33 Hi guys!

Guys, can you please tell me: why do you put support of completely different PCI-E controller into same linux driver?

github.com

torvalds/linux/blob/master/drivers/pci/controller/pcie-mediatek.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek PCIe host controller driver.
 *
 * Copyright (c) 2017 MediaTek Inc.
 * Author: Ryder Lee <[email protected]>
 *	   Honghui Zhang <[email protected]>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/msi.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>

This file has been truncated. show original

sam33 · November 11, 2019, 2:01am

We are still sorting the patches.
It also takes some time to integrate ethernet/switch.

Ryder.Lee · November 11, 2019, 2:48am

No reason. Just share part of probing flow.

ray · November 11, 2019, 7:16am

@Ryder.Lee @sam33 Many thanks!

frank-w · November 11, 2019, 7:20am

You can post patches without ethernet while working on it like ryder did for mt7623. This way we can work on this base. Seems like ray tries to work on pcie/sata/usb. Maybe atf-problem is only on 32bit and at least sd-card is working. Just to avoid redundant work and have same codebase for easier integration.

ray · November 11, 2019, 7:22am

@sam33 I can give you access to my tree, so we will work together on it.

ray · November 12, 2019, 1:40pm

@sam33 @Ryder.Lee Guys, please tell me, is it possible to configure pci-e controller to not make aliases in config space?

Because, currently on every level(top where bridge is and inner where connected device) it respond with same data for all possible slots. So 0/0/0, 0/1/0, 0/2/0 reported as same bridge.

ray · November 19, 2019, 10:08am

@moore @sam33 @Ryder.Lee @sinovoip Hello guys!

I have weird problem, can’t get GPIO90 to hold “1” state.

According to diagram in the manual, actual GPIOs state can be read within DIN even if DIR set to output.

But I always read “0”. (Only on uboot start it read as “1”, any operation make it “0” and no way back)

Already tried many combinations, but no luck.

10211020 DIR3 bit26 to "1"
10211120 DOUT3 bit26 "1"
10211360 MODE6 bits24-27 - tried "1" (and "0", "2")
10211C10 SR bit3 - "0" by default
10211C20 SMT bit3 - "0" by default
10211C30 PU bit3 switched from "1" to "0"
10211C40 PD bit3 - tried both "0" and "1"
10211C60 E4 bit3 - "0" be default
10211C70 E8 bit3 - tried both "0" and "1"

Can you please help me?

moore · November 21, 2019, 3:15am

GPIO 90 is connected to Asmedia chip which is used to switch between PCIe@1,0 and SATA functions. i.e. output-high: PCIe, output-low: SATA. Below is my way to set GPIO90 to high for your reference, thanks.

  pcie_sata_mux_pin_default: pcie_stat_mux_default {
                pins_gpio90 {
                        pinmux = <MT7622_PIN_90_AUXIN3__FUNC_GPIO90>;
                        output-high;
                };
        };

ray · November 21, 2019, 8:37am

Yes, I know that. I use gpio-hog for that:

    asm_sel {
            gpio-hog;
            gpios = <90 GPIO_ACTIVE_HIGH>;
            output-high;
    };

But I want to make a way, to switch that function any time (PCI-E/SATA/SATA-in-PCI-E-slot).

But GPIO90, even whole group 87-90, behave weird. So I want to know:

is there a difference for that GPIOs in hardware?
or how to make it to work correctly, so I will be able to set it in DOUT and read same value from DIN?

Currently I see preloader can set that pin, but from u-boot I can’t.

Maybe, you can give me source of GPIO control of preloader? Think it is not much secret thing

moore · November 22, 2019, 5:11am

AUXIN0 pin = gpio87
AUXIN1 pin = gpio88
AUXIN2 pin = gpio89
AUXIN3 pin = gpio90

and default value of 0x10211CF0 [GPIO_G4_MISC] is 0000000C.

bit3: AUX    IN3 AGPIO Digital Pad Enable
bit2: AUXIN2 AGPIO Digital Pad Enable
bit1: AUXIN1 AGPIO Digital Pad Enable
bit0: AUXIN0 AGPIO Digital Pad Enable
0: Disabled
1: Enabled

so you need to set 0x10211CF0[3:0]=0’b1111 if you want to make gpio87-90 can work at gpio mode, thanks.

ray · November 22, 2019, 7:47am

Thanks a lot, @moore!

I’m tried, still no luck with read back.

But I did test, that makes me sure it works:

U-Boot MT7622> gpio clear 90
gpio: pin 90 (gpio 90) value is 0
U-Boot MT7622> gpio set 90  
gpio: pin 90 (gpio 90) value is 1
   Warning: value of pin is still 0
U-Boot MT7622> gpio clear 90
gpio: pin 90 (gpio 90) value is 0
U-Boot MT7622> scsi scan

If I do reset and run scsi scan, I see no HDD;
If I do reset, clear 90 and run scsi scan, HDD found;
If I do reset, clear 90, set 90 and run scsi scan, I see no HDD;
If I do reset, clear 90, set 90, clear 90 and run scsi scan, HDD found.

Let’s hope we have only two states :)))))

ray · November 26, 2019, 2:28pm

@sinovoip do you able to use PCI-E (not USB with pcie connector) device in pcie1 slot?

I can’t find any proofs that this works for anybody.

Thanks!

UPD: @frank-w tested it and got working module on both slots.

With same SD image my two cards (SATA and WiFi) detected in 1st slot, but not in second

frank-w · November 27, 2019, 12:02pm

have tried now a fullsize card and got same issue like you…it’s recognized on cn25 but not on cn8

if no card is inserted or card is inserted in cn8 lspci does not show pcie host controller, if card is inserted in cn25 i got this output

root@bpi-r64:~# lspci                                                           
00:00.0 PCI bridge: MEDIATEK Corp. Device 3258                                  
01:00.0 Network controller: Qualcomm Atheros QCA986x/988x 802.11ac Wireless Netr
root@bpi-r64:~#

i think at least the first entry should be listed if no card is inserted or card in cn8

if i insert a halfsize-card (intel wifi card with model number: 633ANHMW) in the cn8 it is recognized:

root@bpi-r64:~# lspci                                                           
00:01.0 PCI bridge: MEDIATEK Corp. Device 3258                                  
01:00.0 Network controller: Intel Corporation Centrino Ultimate-N 6300 (rev 35) 
root@bpi-r64:~#

i wonder why pci-bus of the card is same as above because it’s the other slot and pcie-controller bus address differs

but i think we should create a new topic for this pcie-issue

frank-w · December 3, 2019, 7:16am

@sam33 @Ryder.Lee can you give a current state? is there any timeplan?

Ryder.Lee · December 3, 2019, 6:22pm

will submit it before 12/E