Hi. guys.
I based my design sample on the BPI-R64 (MT7622).
Honestly, this was my first time developing on the MT7622 platform, so I copied and pasted the hardware design from the BPI-R64 board. I also used the same key ICs as the BPI-R64 board, such as DDR and eMMC.
However, when I power it on, the following message appears on the serial port and I can’t proceed any further.
F0: 102B 0000
F5: 480A 0031
F5: 480A 0031
F3: 4002 0000
F2: 300C 0000
00: 1005 0000
F5: 480A 0031
F5: 480A 0031
F3: 4002 0000
F2: 300C 0000
01: 102A 0001
02: 1005 0000
BP: 0000 00C0 [0001]
T0: 0000 0311 [000F]
System halt!
So, just in case, I wiped the eMMC on the BPI-R64 board and booted it. The BPI-R64 board progressed to the following:
F0: 102B 0000
F5: 480A 0031
F5: 480A 0031
F3: 0000 0000
V0: 0000 0000 [0001]
00: 0000 0000
BP: 0000 0041 [0000]
G0: 0190 0000
T0: 0000 0395 [000F]
Jump to BL
UNIVPLL_CON0 = 0xFE000000!!!
mt_pll_init: Set pll frequency for 25M crystal
[PMIC_WRAP]wrap_init pass,the return value=0.
[pmic_init] Preloader Start..................
[pmic_init] MT6380 CHIP Code, reg_val = 0, 1:E2 0:E3
[pmic_init] Done...................
Chip part number:7622A
MT7622 Version: 1.2.7, (iPA)
SSC OFF
mt_pll_post_init: mt_get_cpu_freq = 1350000Khz
mt_pll_post_init: mt_get_mem_freq = 1600000Khz
mt_pll_post_init: mt_get_bus_freq = 1119920Khz
[PLFM] Init I2C: OK(0)
[BLDR] Build Time: 20190905-150300
==== Dump RGU Reg ========
RGU MODE: 4D
RGU LENGTH: FFE0
RGU STA: 0
RGU INTERVAL: FFF
RGU SWSYSRST: 8000
==== Dump RGU Reg End ====
RGU: g_rgu_satus:0
mtk_wdt_mode_config mode value=10, tmp:22000010
PL P ON
WDT does not trigger reboot
WDT NONRST=0x20000000
WDT IRQ_EN=0x340003
RGU mtk_wdt_init:MTK_WDT_DEBUG_CTL(590200F3)
[EMI] MDL number = 2
[EMI] DRAMC calibration start
[EMI] DRAMC calibration end
[EMI]rank0 size: 0x40000000
[MEM] complex R/W mem test pass
RAM_CONSOLE wdt status (0x0)=0x0
[mmc_init]: msdc0 start mmc_init_host() in PL...
[msdc_init]: msdc0 Host controller intialization start
[SD0] Pins mode(1), none(0), down(1), up(2), keep(3)
[SD0] Pins mode(2), none(0), down(1), up(2), keep(3)
[info][msdc_set_startbit 1127] read data start bit at rising edge
[info][msdc_config_clksrc] input clock is 400000kHz
[SD0] Bus Width: 1
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1127] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0)
[msdc_init]: msdc0 Host controller intialization done
[mmc_init]: msdc0 start mmc_init_card() in PL...
[mmc_init_card]: start
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1127] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0)
[SD0] Bus Width: 8
[SD0] Switch to High-Speed mode!
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1127] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(2) DDR(1) DIV(192) DS(0) RS(0)
[SD0] Bus Width: 8
[SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0)
[mmc_init_mem_card 3140][SD0] Initialized, eMMC50
before host->cur_bus_clk(259740)
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1127] read data start bit at rising edge
[SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(2) DDR(1) DIV(1) DS(0) RS(0)
host->cur_bus_clk(50000000)
[mmc_init_card]: finish successfully
[PLFM] Init Boot Device: OK(0)
[GPT_PL](BPI)Parsing Primary GPT now...
[GPT_PL]check header, err(signature 0x0000000000000000!=0x5452415020494645)
[GPT_PL]Success to find valid GPT.
[PART] blksz: 512B
[PART] [0x0000000000020000-0x000000000007FFFF] "preloader" (768 blocks)
[PART] [0x0000000000080000-0x00000000000BFFFF] "tee1" (512 blocks)
[PART] [0x00000000000C0000-0x000000000013FFFF] "lk" (1024 blocks)
Device APC domain init setup:
Domain Setup (0x0)
Domain Setup (0x0)
Device APC domain after setup:
Domain Setup (0x0)
Domain Setup (0x0)
[get_part] part->nr_sects=768, part->info->name=preloader
[get_part] part->nr_sects=512, part->info->name=tee1
[get_part] part->nr_sects=1024, part->info->name=lk
load lk (ret=-1)
[BLDR] Second Bootloader Load Failed
PL fatal error..
In my experience, powering on the SoC should perform minimal initialization before accessing storage like eMMC and transferring control to GPT, preloader, APT, uboot, etc. However, this doesn’t seem to be happening.
Is there a specific hardware component I should be debugging?