MxL 1.0.85: three incompatibilities with the mainline DSA driver
I flashed the new mxl862xxc_1030_1085_1085_0069_signed_xfi_upgrade_fca on a BPI-R4 Pro 8X and want to warn people running the mainline/DSA driver rather than BPI’s downstream one. @abs1ck’s report above is on the downstream driver (mxl862xx_dsa-0:00).
Setup: Arch Linux, @frank-w 7.1-main (tip f301d684b889), MxL86252C. The flash itself worked perfectly via the in-kernel devlink dev flash: firmware 1.0.85 (build 85), internal GPHYs 0.77 → 0.105 (0x0069).
Then three separate things broke.
1. XPCS API returns ENOTSUP → switch unreachable
mxl862xx_setup_pcs() selects the firmware XPCS ops at >= 1.0.80. On 1.0.85 those commands do not exist:
mxl862xx mdio-bus:10: configuring for fixed/10gbase-r link mode
mxl862xx mdio-bus:10: CMD 1a03 returned error -134
mxl862xx mdio-bus:10: CMD 1a01 returned error -22
mxl862xx mdio-bus:10: pcs_config failed: -EIO
1a03 is XPCS_PCS_ENABLE; -134 is ENOTSUP in the Zephyr errno space. 1a01/1a02 (PCS_CONFIG/GET_STATE) then fail with -EINVAL, and GET_STATE is polled once per second forever. No SerDes port links, including port 9 — the 10GBASE-R CPU port — so the switch is unreachable from the SoC even though the internal GPHYs link normally.
@dangowrt’s tree already handles this: the gate is at >= 1.0.84, and the XPCS API was renumbered (PCS_ENABLE is gone; +0x7 is now PCS_LINK_UP). frank’s snapshot predates that.
2. PCE rule writes rejected with -1022
mxl862xx mdio-bus:10: CMD 0202 returned error -1022
mxl862xx mdio-bus:10: Unable to use tag protocol "mxl862xx-8021q": -EIO
mxl862xx mdio-bus:10: probe with driver mxl862xx failed with error -5
0202 is TFLOW_PCERULEWRITE. Probe aborts, so zero user ports are registered. Port 0 accepts CTP indices 1–4; port 1 accepts 1–3 and is refused 4 — looks like a reduced or shared per-CTP block rather than a per-port-type limit. Region-0 PCE writes still succeed, so struct mxl862xx_pce_rule is unchanged.
Again already fixed upstream of frank: @dangowrt added PCERULELOGICWRITE gated at >= 1.0.83, where the firmware grows the per-CTP block on demand instead of indexing a fixed one.
3. tag_8021q stops forwarding
With dsa-tag-protocol = "mxl862xx-8021q" on 1.0.85, probe completes, every port links, bridge ports reach forwarding — and nothing passes. Conduit capture shows the tags are correct in both directions (per-port VIDs 3074/3075/3085, stripped properly). Disabling bridge VLAN filtering changes nothing.
Switching the same running kernel to the native tag restores forwarding on the SerDes port immediately:
echo mxl862xx > /sys/class/net/<conduit>/dsa/tagging
Still unsolved: GPHY ingress is dead!
The four internal 2.5G copper ports receive nothing, in either tag mode. Switch-side RMON (ethtool -S) on a port with a 1G client and carrier up for minutes:
tx_packets: 8439 rx_packets: 0 rx_bytes: 0
TxAcmDroppedPkts: 0 RxFilteredPkts: 0 RxExtendedVlanDiscardPkts: 0
MtuExceedDiscardPkts: 0 RxBadBytes: 0
Every discard counter is zero — frames never reach the switch MAC at all. The SerDes port on the same switch shows normal RX plus non-zero RxFilteredPkts/RxBadBytes.
@dangowrt’s mxl-gpy.c carries a link_change_notify hook that force-sets VSPEC1_SGMII_CTRL_ANEN on every link change, with the comment “setting SGMII AN to enabled then back to disabled clears this for some reason” — same symptom, no root cause. I reproduced the register state (VSPEC1_SGMII_CTRL = 0x0008, ANEN clear, at a 1G link) and tried setting ANEN, ANEN+ANRS, and the enable→disable toggle by hand. The writes stick (read back correctly, firmware does not fight them) but RX stays at 0. So on this firmware it is not simply the ANEN bit.
Summary
@frank-w — would a resync of drivers/net/dsa/mxl862xx/ (and the mxl-gpy delta) from @dangowrt’s tree be on the cards? Happy to test and send a PR if useful.
@dangowrt — the GPHY ingress failure above may be a cleaner reproduction of whatever your link_change_notify hack is papering over, if that’s of any use. Full logs, conduit captures and RMON dumps available on request.
@pameruoso — you mentioned dumping your 1.0.70 off the QSPI with flashrom and getting a matching SHA five times. Would you be willing to share it? No public 1.0.70 image exists and BPI has declined to provide one, so it is currently the only known rollback for anyone who hits this. (Also interested in how you’d restore it — the published upgrade image has an MCUboot header and two CRC’d slots, which a raw chip dump won’t match.)