Also OpenWrt uses probing within U-Boot to communicate the position of switch
D to OpenWrt/Linux (by selecting the appropriate device tree overlay).
While in theory it would be possible to have both, NAND and NOR connected in a usable way at the same time on the same bus (using SPI chip-select lines), this is not how it works on the BPi-R3.
C is in position 1 for NAND, you won’t be able to access NOR at all.
C is in position 0 for NOR, you won’t be able to access NAND at all.
This is because both devices use the same chip-select line, and sadly instead of having two chip-select lines (CS0 and CS1) and using the dip switch
C to swap CS0 and CS1, the dip switch directly selects which of the two is connected to CS0 (and there is no CS1 at all). So this was a decision of the board designers, supposedly to not waste an additional SoC pin for CS1 and in order not to need another multiplexer IC for swapping CS0 and CS1.
A similar situation applies for eMMC vs. microSD, also here you can only use one of them at the time, this time a multiplexer IC is used, but it switches the first 4 data lines to be connected either to microSD or to the eMMC.
To also answer your question, applying the restrictions explained above, the Linux device names of each storage chip are: