[BPI-R3] kernel fails setting EMMC clock to 416M, depends on U-Boot

I’m still working on my own install of Arch Linux on the R3.

I can use the emmc on HS200 ok (even write it without using NAND/NOR image), but…

on HS400 I get the following:

[  133.416314] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  133.426428] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  133.436566] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  133.540762] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  133.551996] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  133.562159] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  133.567923] I/O error, dev mmcblk0, sector 10038120 op 0x1:(WRITE) flags 0x104000 phys_seg 123 prio class 2
[  133.568168] I/O error, dev mmcblk0, sector 10039144 op 0x1:(WRITE) flags 0x100000 phys_seg 73 prio class 2

[  148.533725] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.544168] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.554497] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.564559] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.570331] I/O error, dev mmcblk0, sector 1115648 op 0x1:(WRITE) flags 0x800 phys_seg 87 prio class 2
[  148.584183] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.594287] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.604389] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.608827] F2FS-fs (mmcblk0p3): do_checkpoint failed err:-5, stop checkpoint
[  148.614491] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.627342] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.637446] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.647547] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.657648] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.667613] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.677575] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.687536] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.697445] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.707408] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.717369] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.727337] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.737299] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.747260] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.753031] I/O error, dev mmcblk0, sector 248464 op 0x1:(WRITE) flags 0x3800 phys_seg 1 prio class 2
[  148.766411] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.772179] I/O error, dev mmcblk0, sector 160432 op 0x1:(WRITE) flags 0x3800 phys_seg 1 prio class 2
[  148.785497] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.791272] I/O error, dev mmcblk0, sector 159904 op 0x1:(WRITE) flags 0x3800 phys_seg 1 prio class 2
[  148.804649] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.810419] I/O error, dev mmcblk0, sector 155800 op 0x1:(WRITE) flags 0x3800 phys_seg 1 prio class 2
[  148.823791] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.829561] I/O error, dev mmcblk0, sector 155648 op 0x1:(WRITE) flags 0x3800 phys_seg 1 prio class 2
[  148.842942] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.848699] I/O error, dev mmcblk0, sector 151552 op 0x1:(WRITE) flags 0x3800 phys_seg 1 prio class 2
[  148.862073] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[  148.867831] I/O error, dev mmcblk0, sector 147784 op 0x1:(WRITE) flags 0x3800 phys_seg 2 prio class 2
[  148.877190] I/O error, dev mmcblk0, sector 143360 op 0x1:(WRITE) flags 0x3800 phys_seg 3 prio class 2

the overlay (applied to the main dtb at fip-image build time):

/dts-v1/;
/plugin/;

&mmc0 {
  bus-width = <8>;
  max-frequency = <200000000>;
  cap-mmc-highspeed;
  mmc-hs200-1_8v;
//  mmc-hs400-1_8v;
//  hs400-ds-delay = <0x14014>;
  non-removable;
  no-sd;
  no-sdio;
  status = "okay";
};

kernel = mainline linux rolling stable 6.2.7

Anyone have any ideas why this is happening? I think it happens after writing…

PS: plugin is new style, compare it with old style using

dtc -I dts -O dts emmc-enable.dts

Maybe any of the existing sd-card options preventing this? As you add only emmc specific properties and not deleting the sd-only props. Afair my dto was working without issues,but my last emmc test was last year :stuck_out_tongue:

How does your full mmc node looks like?

dtc -I fs -O dts /sys/firmware/devicetree/base | less

When only booting with HS200, it looks like this:

                mmc@11230000 {
                        pinctrl-names = "default\0state_uhs";
                        pinctrl-0 = <0x0e>;
                        clock-names = "source\0hclk\0source_cg\0bus_clk\0sys_cg";
                        vqmmc-supply = <0x11>;
                        mmc-hs200-1_8v;
                        bus-width = <0x08>;
                        non-removable;
                        no-sdio;
                        interrupts = <0x00 0x8f 0x04>;
                        clocks = <0x04 0x23 0x03 0x29 0x03 0x28 0x03 0x2a 0x03  0x2b>;
                        vmmc-supply = <0x10>;
                        no-sd;
                        compatible = "mediatek,mt7986-mmc";
                        pinctrl-1 = <0x0f>;
                        status = "okay";
                        reg = <0x00 0x11230000 0x00 0x1000 0x00 0x11c20000 0x00 0x1000>;
                        phandle = <0x3f>;
                        max-frequency = <0xbebc200>;
                        cap-mmc-highspeed;
                };

When I add

  mmc-hs400-1_8v;
  hs400-ds-delay = <0x14014>;

Then root does not get r/w but read only and the boot sequence fails…

[    5.970860] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    5.978756] I/O error, dev mmcblk0, sector 1111952 op 0x1:(WRITE) flags 0x2800 phys_seg 1 prio class 2
[    5.992288] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.003450] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.013364] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.020921] I/O error, dev mmcblk0, sector 1111952 op 0x1:(WRITE) flags 0x800 phys_seg 1 prio class 2
[    6.034181] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.047176] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.057248] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.067028] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.076884] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.086787] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.096630] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.106468] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.116310] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.126154] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.136011] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.145849] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.151626] I/O error, dev mmcblk0, sector 1121704 op 0x1:(WRITE) flags 0x800 phys_seg 1 prio class 2
[    6.151783] I/O error, dev mmcblk0, sector 1076984 op 0x1:(WRITE) flags 0x800 phys_seg 1 prio class 2
[    6.173845] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.183684] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414
[    6.188769] F2FS-fs (mmcblk0p3): do_checkpoint failed err:-5, stop checkpoint
[    6.189449] I/O error, dev mmcblk0, sector 1121712 op 0x1:(WRITE) flags 0x800 phys_seg 1 prio class 2
[    6.189621] I/O error, dev mmcblk0, sector 147480 op 0x1:(WRITE) flags 0x3800 phys_seg 1 prio class 2
[    6.196844] systemd-journald[1477]: Failed to open system journal: Input/output error
[    6.209613] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x15414

I can run ash from initrd to get the devicetree, the devicetree looks like this:

         mmc@11230000 {
                        pinctrl-names = "default\0state_uhs";
                        pinctrl-0 = <0x0e>;
                        clock-names = "source\0hclk\0source_cg\0bus_clk\0sys_cg";
                        vqmmc-supply = <0x11>;
                        mmc-hs200-1_8v;
                        bus-width = <0x08>;
                        non-removable;
                        no-sdio;
                        mmc-hs400-1_8v;
                        interrupts = <0x00 0x8f 0x04>;
                        clocks = <0x04 0x23 0x03 0x29 0x03 0x28 0x03 0x2a 0x03 0x2b>;
                        hs400-ds-delay = <0x14014>;
                        vmmc-supply = <0x10>;
                        no-sd;
                        compatible = "mediatek,mt7986-mmc";
                        pinctrl-1 = <0x0f>;
                        status = "okay";
                        reg = <0x00 0x11230000 0x00 0x1000 0x00 0x11c20000 0x00 0x1000>;
                        phandle = <0x3f>;
                        max-frequency = <0xbebc200>;
                        cap-mmc-highspeed;
                };

I only used the SD -> EMMC trick to get the image on emmc. I’m now just using one dtb and directly booting from emmc…

[some text removed that has nothing to do with this bug]

Looking at /drivers/mmc/host/mtk-sd.c, I guess the retuning is flagged by crc errors:

void mmc_request_done(struct mmc_host *host, struct mmc_request *mrq)
{
	struct mmc_command *cmd = mrq->cmd;
	int err = cmd->error;

	/* Flag re-tuning needed on CRC errors */
	if (!mmc_op_tuning(cmd->opcode) &&
	    !host->retune_crc_disable &&
	    (err == -EILSEQ || (mrq->sbc && mrq->sbc->error == -EILSEQ) ||
	    (mrq->data && mrq->data->error == -EILSEQ) ||
	    (mrq->stop && mrq->stop->error == -EILSEQ)))
		mmc_retune_needed(host);

from dynamic debugging I get:

[   26.397388] mmc0: starting CMD8 arg 00000000 flags 000000b5
[   26.402957] mmc0:     blksz 512 blocks 1 flags 00000200 tsac 150 ms nsac 0
[   26.409836] mtk-msdc 11230000.mmc: msdc_irq: events=00000100
[   26.415488] mtk-msdc 11230000.mmc: DMA start
[   26.419742] mtk-msdc 11230000.mmc: msdc_start_data: cmd=8 DMA data: 1 blocks; read=1
[   26.427466] mtk-msdc 11230000.mmc: msdc_irq: events=00008000
[   26.433109] mtk-msdc 11230000.mmc: DMA status: 0x       7
[   26.438491] mtk-msdc 11230000.mmc: DMA stop
[   26.442659] mtk-msdc 11230000.mmc: interrupt events: 8000
[   26.448044] mtk-msdc 11230000.mmc: msdc_data_xfer_done: cmd=8; blocks=1
[   26.454641] mtk-msdc 11230000.mmc: data_error=-84 xfer_size=0
[   26.460369] mtk-msdc 11230000.mmc: msdc_track_cmd_data: cmd=8 arg=00000000; host->error=0x00000004
[   26.469309] mmc0: req done (CMD8): 0: 00000900 00000000 00000000 00000000
[   26.476078] mmc0:     0 bytes transferred: -84

It happens after:

[   26.111414] mmc0: clock 52000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 10

changes to

[   26.129676] mmc0: clock 200000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 10

So after clock goes up to 200Mz

EILSEQ = 84, so

			if (events & MSDC_INT_DATTMO)
				data->error = -ETIMEDOUT;
			else if (events & MSDC_INT_DATCRCERR)
				data->error = -EILSEQ;

			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
				__func__, mrq->cmd->opcode, data->blocks);
			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
				(int)data->error, data->bytes_xfered);

Indeed, MSDC_INT_DATCRCERR events.

Edit: I have also checked, I use a trick to boot from emmc mmcblk0, instead of mmcblk0boot0. So I tried it without this trick, but still the same errors.

Edit2: I’ve tried:

  hs400-ds-delay = <0x15414>;

But still the same result.

Edit3: Since I’m using a modified ATF, I have tried the original atf mtksoc branch, with only the minimum changes to boot a kernel directly, I have it here: https://github.com/ericwoud/arm-trusted-firmware/commits/mtksoc-r3kernel But sadly, this also does not make any difference. I don’t believe it is ATF related.

Edit4: I have also tried the (def)config from the bpi bsp 5.15 (on the 6.2.8 kernel), but still the same result.

I have not tried it with U-Boot in the bootchain, but the kernel drivers should not depend on U-Boot for the correct initialization. I see in uboot/configs/mt7986a_bpir3_emmc_defconfig only CONFIG_MMC_HS200_SUPPORT is set.

Since now that I can toggle using uboot, only adding or removing a package,

I thought I would give it a try, HS400 with u-boot in the bootchain, and kernel v6.3.6

Indeed, without uboot I get the errors, and with uboot no errors.

Conclusion:

The kernel driver depends on U-Boot for correct initialization of the mmc (host?) driver… Which it should not.

@frank-w or @sam33 have any idea why?

With the help of debugging, I have narrowed it down a bit:

It seems that the kernel depends on U-Boot to setup the source clock correctly.

Without U-Boot:

[   14.749160] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 0
[   14.756807] mtk-msdc 11230000.mmc: Bus Width = 3
[   14.761408] mmc0: starting CMD8 arg 00000000 flags 000000b5
[   14.766969] mmc0:     blksz 512 blocks 1 flags 00000200 tsac 150 ms nsac 0
[   14.774129] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   14.779778] mtk-msdc 11230000.mmc: DMA start
[   14.784032] mtk-msdc 11230000.mmc: msdc_start_data: cmd=8 DMA data: 1 blocks; read=1
[   14.791754] mtk-msdc 11230000.mmc: msdc_irq: events=00003040
[   14.797395] mtk-msdc 11230000.mmc: DMA status: 0x       6
[   14.802778] mtk-msdc 11230000.mmc: DMA stop
[   14.806945] mmc0: req done (CMD8): 0: 00000900 00000000 00000000 00000000
[   14.813713] mmc0:     512 bytes transferred: 0
[   14.818151] mmc0: starting CMD6 arg 03b90201 flags 0000049d
[   14.824009] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   14.829652] mmc0: req done (CMD6): 0: 00000800 00000000 00000000 00000000
[   14.836429] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 9
[   14.844067] mtk-msdc 11230000.mmc: Bus Width = 3
[   14.848696] mtk-msdc 11230000.mmc: sclk: 400000, timing: 9
[   14.854163] mmc0: clock 52000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 9
[   14.861980] mtk-msdc 11230000.mmc: Bus Width = 3
[   14.866626] mtk-msdc 11230000.mmc: sclk: 40000000, timing: 9
[   14.872268] mmc0: starting CMD13 arg 00010000 flags 00000195
[   14.877925] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   14.883568] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 00000000
[   14.890433] mmc0: clock 200000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 9
[   14.898339] mtk-msdc 11230000.mmc: Bus Width = 3
[   14.902950] mtk-msdc 11230000.mmc: sclk: 40000000, timing: 9

[   16.754042] mmc0: clock 200000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 1
[   16.761948] mtk-msdc 11230000.mmc: Bus Width = 3
[   16.766565] mtk-msdc 11230000.mmc: sclk: 40000000, timing: 1
[   16.772206] mmc0: clock 52000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 1
[   16.780022] mtk-msdc 11230000.mmc: Bus Width = 3
[   16.784633] mtk-msdc 11230000.mmc: sclk: 40000000, timing: 1
[   16.790280] mmc0: starting CMD13 arg 00010000 flags 00000195
[   16.795939] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   16.801581] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 00000000
[   16.808446] mmc0: starting CMD6 arg 03b70601 flags 0000049d
[   16.814012] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   16.819655] mmc0: req done (CMD6): 0: 00000800 00000000 00000000 00000000
[   16.826434] mmc0: starting CMD13 arg 00010000 flags 00000195
[   16.832085] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   16.837728] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 00000000
[   16.844594] mmc0: starting CMD6 arg 03b90301 flags 0000049d
[   16.850169] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   16.855812] mmc0: req done (CMD6): 0: 00000800 00000000 00000000 00000000
[   16.862589] mmc0: clock 52000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 10
[   16.870496] mtk-msdc 11230000.mmc: Bus Width = 3
[   16.875108] mtk-msdc 11230000.mmc: sclk: 20000000, timing: 10
[   16.880842] mmc0: clock 200000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 10
[   16.888831] mtk-msdc 11230000.mmc: Bus Width = 3
[   16.893442] mtk-msdc 11230000.mmc: sclk: 20000000, timing: 10

With U-Boot:

[   18.586262] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 0
[   18.593908] mtk-msdc 11230000.mmc: Bus Width = 3
[   18.598509] mmc0: starting CMD8 arg 00000000 flags 000000b5
[   18.604070] mmc0:     blksz 512 blocks 1 flags 00000200 tsac 150 ms nsac 0
[   18.611228] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   18.616877] mtk-msdc 11230000.mmc: DMA start
[   18.621130] mtk-msdc 11230000.mmc: msdc_start_data: cmd=8 DMA data: 1 blocks; read=1
[   18.628853] mtk-msdc 11230000.mmc: msdc_irq: events=00003040
[   18.634494] mtk-msdc 11230000.mmc: DMA status: 0x       6
[   18.639876] mtk-msdc 11230000.mmc: DMA stop
[   18.644043] mmc0: req done (CMD8): 0: 00000900 00000000 00000000 00000000
[   18.650812] mmc0:     512 bytes transferred: 0
[   18.655249] mmc0: starting CMD6 arg 03b90201 flags 0000049d
[   18.661103] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   18.666745] mmc0: req done (CMD6): 0: 00000800 00000000 00000000 00000000
[   18.673522] mmc0: clock 400000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 9
[   18.681160] mtk-msdc 11230000.mmc: Bus Width = 3
[   18.685786] mtk-msdc 11230000.mmc: sclk: 400000, timing: 9
[   18.691255] mmc0: clock 52000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 9
[   18.699071] mtk-msdc 11230000.mmc: Bus Width = 3
[   18.703713] mtk-msdc 11230000.mmc: sclk: 52000000, timing: 9
[   18.709354] mmc0: starting CMD13 arg 00010000 flags 00000195
[   18.715010] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   18.720654] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 00000000
[   18.727519] mmc0: clock 200000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 9
[   18.735426] mtk-msdc 11230000.mmc: Bus Width = 3
[   18.740035] mtk-msdc 11230000.mmc: sclk: 104000000, timing: 9

[   20.591002] mmc0: clock 200000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 1
[   20.598908] mtk-msdc 11230000.mmc: Bus Width = 3
[   20.603523] mtk-msdc 11230000.mmc: sclk: 104000000, timing: 1
[   20.609251] mmc0: clock 52000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 1
[   20.617068] mtk-msdc 11230000.mmc: Bus Width = 3
[   20.621676] mtk-msdc 11230000.mmc: sclk: 52000000, timing: 1
[   20.627323] mmc0: starting CMD13 arg 00010000 flags 00000195
[   20.632972] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   20.638614] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 00000000
[   20.645479] mmc0: starting CMD6 arg 03b70601 flags 0000049d
[   20.651043] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   20.656685] mmc0: req done (CMD6): 0: 00000800 00000000 00000000 00000000
[   20.663463] mmc0: starting CMD13 arg 00010000 flags 00000195
[   20.669113] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   20.674755] mmc0: req done (CMD13): 0: 00000900 00000000 00000000 00000000
[   20.681619] mmc0: starting CMD6 arg 03b90301 flags 0000049d
[   20.687193] mtk-msdc 11230000.mmc: msdc_irq: events=00002140
[   20.692836] mmc0: req done (CMD6): 0: 00000800 00000000 00000000 00000000
[   20.699614] mmc0: clock 52000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 10
[   20.707521] mtk-msdc 11230000.mmc: Bus Width = 3
[   20.712130] mtk-msdc 11230000.mmc: sclk: 52000000, timing: 10
[   20.717865] mmc0: clock 200000000Hz busmode 2 powermode 2 cs 0 Vdd 21 width 8 timing 10
[   20.725855] mtk-msdc 11230000.mmc: Bus Width = 3
[   20.730463] mtk-msdc 11230000.mmc: sclk: 104000000, timing: 10

And here are the differences:

Without U-Boot, but with CRC errors:

[   14.848696] mtk-msdc 11230000.mmc: sclk: 400000, timing: 9
[   14.866626] mtk-msdc 11230000.mmc: sclk: 40000000, timing: 9
[   14.902950] mtk-msdc 11230000.mmc: sclk: 40000000, timing: 9
[   16.766565] mtk-msdc 11230000.mmc: sclk: 40000000, timing: 1
[   16.784633] mtk-msdc 11230000.mmc: sclk: 40000000, timing: 1
[   16.875108] mtk-msdc 11230000.mmc: sclk: 20000000, timing: 10
[   16.893442] mtk-msdc 11230000.mmc: sclk: 20000000, timing: 10

With U-Boot, but without CRC errors:

[   18.685786] mtk-msdc 11230000.mmc: sclk: 400000, timing: 9
[   18.703713] mtk-msdc 11230000.mmc: sclk: 52000000, timing: 9
[   18.740035] mtk-msdc 11230000.mmc: sclk: 104000000, timing: 9
[   20.603523] mtk-msdc 11230000.mmc: sclk: 104000000, timing: 1
[   20.621676] mtk-msdc 11230000.mmc: sclk: 52000000, timing: 1
[   20.712130] mtk-msdc 11230000.mmc: sclk: 52000000, timing: 10
[   20.730463] mtk-msdc 11230000.mmc: sclk: 104000000, timing: 10

So the sclk clock is different when starting with U-Boot and without U-Boot

How to setup the sourceclock, so that it will set the correct frequency? Can this be fixed in the devicetree?

Edit:

clk_get_rate(host->src_clk) returns different values. Calculation of sclk depends on this.

Without U-Boot:

clk_get_rate(host->src_clk) returns 40000000

With U-Boot:

clk_get_rate(host->src_clk) returns 416000000

Notice a factor 10.4 difference.

It means that the kernel fails to set the clock to 416M. Correct functioning of the mmc-host relies on U-Boot to set the clock at 416M.

I have changed the topic accordingly.

Edit2:

Is it possible to set the rate via devicetree with assigned-clocks and assigned-clock-rates ?

Edit3:

Yup. Adding the following:

&mmc0 {
  assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>;
  assigned-clock-rates = <416000000>;
};

Makes clk_get_rate(host->src_clk) return 416000000, even if U-Boot is not in the bootchain. I checked, also no more CRC errors.

@frank-w I’m am still not sure why the clock rate needs to be set in the devicetree, and if this i a good fix or only hiding the symptom of a real bug? What do you think?

Afair the clock-structure is differently in uboot and linux.

Thx for debugging this,but i think only @dangowrt or mtk (@sam33,@hackpascal) can correctly answer this

I guess the settings are not upstreamable this way as properties not allowed in bindings:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/mtk-sd.yaml

For me it looks like a bug in clock driver as 416m is assigned

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt7986a.dtsi#n354

The assigned-clocks properties can be bound to any node if I understand correctly, so upstreaming I think is not a problem.

I am not sure however if this is the solution which would be preferred, or another solution needs to be found.

The 416M clock is present in the devicetree as one of the clocks on the mmc controller, but it is never set to 416M by the kernel, unless it is added extra to the devicetree, or perhapse some bug fixed.

Maybe one of the guys above can shed some light on this…

Thanks for debugging, we can add the missing assigned-clocks and assigned-clock-parents nodes back to Linux to update the clock rate of CLK_TOP_EMMC_416M_SEL and CLK_TOP_EMMC_250M_SEL like we did in the u-boot (https://github.com/u-boot/u-boot/blob/50842b217fef505a0ec6662cc2acdc55d0bb23c5/arch/arm/dts/mt7986.dtsi#L287) But the clock naming is a bit different because the clock drivers are different, you can try to set the clock parent of CLK_TOP_EMMC_416M_SEL to <&apmixedsys CLK_APMIXED_MPLL> and set the clock parent of CLK_TOP_EMMC_250M_SEL to <&topckggen CLK_TOP_NET1PLL_D5_D2>

That sounds good.

Indeed I was checking all clocks with:

cat /sys/kernel/debug/clk/clk_summary

and just about to add that also the 250M clock is set at 40M without U-Boot. I have found no further differences in any of the clock rates, comparing with/without U-Boot.

Further I have found that only using:

&mmc0 {
  assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>;
  assigned-clock-rates = <416000000>;
};

seems to take care of all differences (on 416M clock that is). I have not used assigned-clock-parents and it does not seem to be necessary to take care of all the differences in clk_summary

Also I thought the parents are set in clk-mt7986-topckgen.c https://elixir.bootlin.com/linux/latest/source/drivers/clk/mediatek/clk-mt7986-topckgen.c#L104

From the tree of clk_summary I find that parents seem already correctly setup to the system:

Without fix:

                                  enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 clkxtal                              8        8        0    40000000          0     0  50000         Y
    top_jtag                          0        0        0    50000000          0     0  50000         Y
       arm_db_jtsel                   0        0        0    50000000          0     0  50000         N
    top_xtal                          9        9        0    40000000          0     0  50000         Y
       infra_ipcie_pipe               0        0        0    40000000          0     0  50000         N
       emmc_416m_sel                  0        0        0    40000000          0     0  50000         N
          infra_msdc                  0        0        0    40000000          0     0  50000         N
       emmc_250m_sel                  0        0        0    40000000          0     0  50000         N
          infra_msdc_hck              0        0        0    40000000          0     0  50000         N
       uart_sel                       1        1        0    40000000          0     0  50000         Y
          infra_uart0_sel             1        1        0    40000000          0     0  50000         Y
             infra_uart0              1        1        0    40000000          0     0  50000         Y
       spinfi_sel                     0        0        0    40000000          0     0  50000         N
          infra_spinfi1               0        0        0    40000000          0     0  50000         N
       top_rtc_32p7k                  0        0        0       32786          0     0  50000         Y
       top_rtc_32k                    0        0        0       32000          0     0  50000         Y
          infra_frtc                  0        0        0       32000          0     0  50000         N
       top_xtal_d2                    0        0        0    20000000          0     0  50000         Y
       sgmii0_tx250m_en               1        1        0    40000000          0     0  50000         Y
       sgmii0_rx250m_en               1        1        0    40000000          0     0  50000         Y
       sgmii0_cdr_ref                 1        1        0    40000000          0     0  50000         Y
       sgmii0_cdr_fb                  1        1        0    40000000          0     0  50000         Y
       sgmii1_tx250m_en               1        1        0    40000000          0     0  50000         Y
       sgmii1_rx250m_en               1        1        0    40000000          0     0  50000         Y
       sgmii1_cdr_ref                 1        1        0    40000000          0     0  50000         Y
       sgmii1_cdr_fb                  1        1        0    40000000          0     0  50000         Y
    apll2                             0        0        0   196608000          0     0  50000         Y
       aud_l_sel                      0        0        0   196608000          0     0  50000         N
          infra_aud_l                 0        0        0   196608000          0     0  50000         N
       top_apll2_d4                   0        0        0    49152000          0     0  50000         Y
          a_tuner_sel                 0        0        0    49152000          0     0  50000         N
             infra_aud_eg2            0        0        0    49152000          0     0  50000         N
          a1sys_sel                   0        0        0    49152000          0     0  50000         N
             infra_aud_aud            0        0        0    49152000          0     0  50000         N
    mpll                              3        3        0   416000000          0     0  50000         Y
       top_mpll_d3_d2                 1        1        0    69333333          0     0  50000         Y
          sysapb_sel                  1        1        0    69333333          0     0  50000         Y
       top_mpll_d8_d2                 4        4        0    26000000          0     0  50000         Y
          u2u3_sel                    1        1        0    26000000          0     0  50000         Y
             infra_iusb               1        1        0    26000000          0     0  50000         Y
          csw_f26m_sel                1        1        0    26000000          0     0  50000         Y
             infra_ipcier             0        0        0    26000000          0     0  50000         N
             infra_adc_frc            0        0        0    26000000          0     0  50000         N
                infra_adc_26m         0        0        0    26000000          0     0  50000         N
             infra_therm              0        0        0    26000000          0     0  50000         N
             infra_sej_13m            0        0        0    26000000          0     0  50000         N
             infra_dramc_26m          0        0        0    26000000          0     0  50000         N
             infra_aud_26m            0        0        0    26000000          0     0  50000         N
             infra_uart2_sel          0        0        0    26000000          0     0  50000         Y
                infra_uart2           0        0        0    26000000          0     0  50000         N
             infra_uart1_sel          0        0        0    26000000          0     0  50000         Y
                infra_uart1           0        0        0    26000000          0     0  50000         N
          usb3_phy_sel                1        1        0    26000000          0     0  50000         Y
          pcie_phy_sel                0        0        0    26000000          0     0  50000         N
          dramc_sel                   1        1        0    26000000          0     0  50000         Y
          f_26m_adc_sel               0        0        0    26000000          0     0  50000         N
       top_mpll_d8                    0        0        0    52000000          0     0  50000         Y
       top_mpll_d4                    0        0        0   104000000          0     0  50000         Y
       top_mpll_d2                    1        1        0   208000000          0     0  50000         Y
          spim_mst_sel                0        0        0   208000000          0     0  50000         N
          spi_sel                     0        0        0   208000000          0     0  50000         N
             infra_spi1_sel           0        0        0   208000000          0     0  50000         Y
                infra_spi1            0        0        0   208000000          0     0  50000         N
             infra_spi0_sel           0        0        0   208000000          0     0  50000         Y
                infra_spi0            0        0        0   208000000          0     0  50000         N
          dramc_md32_sel              1        1        0   208000000          0     0  50000         Y
    net1pll                           4        4        0  2500000000          0     0  50000         Y
       top_net1pll_d8_d4              2        2        0    78125000          0     0  50000         Y
          ap2cnn_host_sel             1        1        0    78125000          0     0  50000         Y
          sgm_reg_sel                 1        1        0    78125000          0     0  50000         Y
       top_net1pll_d8_d2              1        1        0   156250000          0     0  50000         Y
          sysaxi_sel                  3        3        0   156250000          0     0  50000         Y
             infra_ipcieb             0        0        0   156250000          0     0  50000         N
             infra_iusb_133           1        1        0   156250000          0     0  50000         Y
             infra_msdc_133m          0        0        0   156250000          0     0  50000         N
             infra_trng               0        0        0   156250000          0     0  50000         N
             infra_aud_bus            0        0        0   156250000          0     0  50000         N
             infra_cq_dma             0        0        0   156250000          0     0  50000         N
             infra_sysaxi_d2          2        3        0    78125000          0     0  50000         Y
                infra_iusb_66m        1        1        0    78125000          0     0  50000         Y
                infra_msdc_66m        1        1        0    78125000          0     0  50000         Y
                infra_spi1_hck        0        0        0    78125000          0     0  50000         N
                infra_spi0_hck        0        0        0    78125000          0     0  50000         N
                infra_nfi_hck         0        0        0    78125000          0     0  50000         N
                infra_sej             0        0        0    78125000          0     0  50000         N
                infra_ap_dma          0        1        0    78125000          0     0  50000         N
                infra_dbg             0        0        0    78125000          0     0  50000         N
                infra_pwm_hck         0        0        0    78125000          0     0  50000         N
                infra_gpt_sta         0        0        0    78125000          0     0  50000         N
          pwm_sel                     0        0        0   156250000          0     0  50000         N
             infra_pwm_bsel           0        0        0   156250000          0     0  50000         Y
                infra_pwm_sta         0        0        0   156250000          0     0  50000         N
             infra_pwm2_sel           0        0        0   156250000          0     0  50000         Y
                infra_pwm2            0        0        0   156250000          0     0  50000         N
             infra_pwm1_sel           0        0        0   156250000          0     0  50000         Y
                infra_pwm1            0        0        0   156250000          0     0  50000         N
       top_net1pll_d5_d4              2        3        0   125000000          0     0  50000         Y
          u2u3_xhci_sel               1        1        0   125000000          0     0  50000         Y
          u2u3_sys_sel                1        1        0   125000000          0     0  50000         Y
             infra_iusb_sys           1        1        0   125000000          0     0  50000         Y
          pextp_tl_ck_sel             0        0        0   125000000          0     0  50000         N
             infra_ipcie              0        0        0   125000000          0     0  50000         N
             infra_pcie_sel           0        0        0   125000000          0     0  50000         Y
          i2c_sel                     0        1        0   125000000          0     0  50000         N
             infra_i2c0               0        1        0   125000000          0     0  50000         N
       top_net1pll_d5_d2              0        0        0   250000000          0     0  50000         Y
       top_net1pll_d5                 1        1        0   500000000          0     0  50000         Y
          netsys_500m_sel             1        1        0   500000000          0     0  50000         Y
       top_net1pll_d4                 0        0        0   625000000          0     0  50000         Y
    wedmcupll                         1        1        0   760000000          0     0  50000         Y
       netsys_mcu_sel                 2        2        0   760000000          0     0  50000         Y
          eth_wocpu1_en               1        1        0   760000000          0     0  50000         Y
          eth_wocpu0_en               1        1        0   760000000          0     0  50000         Y
       top_wedmcupll_d5_d2            0        0        0    76000000          0     0  50000         Y
    sgmpll                            1        1        0   325000000          0     0  50000         Y
       sgm_325m_sel                   2        2        0   325000000          0     0  50000         Y
          eth_gp2_en                  1        1        0   325000000          0     0  50000         Y
          eth_gp1_en                  1        1        0   325000000          0     0  50000         Y
    mmpll                             3        3        0  1440000000          0     0  50000         Y
       top_mmpll_u2phy                2        2        0    48000000          0     0  50000         Y
          da_u2_ck_1p_sel             2        2        0    48000000          0     0  50000         Y
          da_u2_refsel                2        2        0    48000000          0     0  50000         Y
       top_mmpll_d3_d8                0        0        0    60000000          0     0  50000         Y
       top_mmpll_d8_d2                0        0        0    90000000          0     0  50000         Y
       top_mmpll_d8                   0        0        0   180000000          0     0  50000         Y
          nfi1x_sel                   0        0        0   180000000          0     0  50000         N
             infra_fbist2fpc          0        0        0   180000000          0     0  50000         N
             infra_nfi1               0        0        0   180000000          0     0  50000         N
       top_mmpll_d4                   1        1        0   360000000          0     0  50000         Y
          netsys_sel                  1        1        0   360000000          0     0  50000         Y
       top_mmpll_d2                   1        1        0   720000000          0     0  50000         Y
          conn_mcusys_sel             1        1        0   720000000          0     0  50000         Y
    net2pll                           1        1        0   800000000          0     0  50000         Y
       eip_b_sel                      0        0        0   800000000          0     0  50000         N
          infra_eip97                 0        0        0   800000000          0     0  50000         N
       netsys_2x_sel                  1        1        0   800000000          0     0  50000         Y
          eth_fe_en                   1        1        0   800000000          0     0  50000         Y
       top_net2pll_d3_d2              0        0        0   400000000          0     0  50000         Y
          arm_db_main_sel             0        0        0   400000000          0     0  50000         N
       top_net2pll_d4_d2              0        0        0   100000000          0     0  50000         Y
       top_net2pll_d4                 0        0        0   200000000          0     0  50000         Y
    armpll                            1        1        0  2000000000          0     0  50000         Y

With fix 416M in devicetree (clocks+rate, not parents)

                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
 clkxtal                              8        8        0    40000000          0     0  50000         Y
    top_jtag                          0        0        0    50000000          0     0  50000         Y
       arm_db_jtsel                   0        0        0    50000000          0     0  50000         N
    top_xtal                          9        9        0    40000000          0     0  50000         Y
       infra_ipcie_pipe               0        0        0    40000000          0     0  50000         N
       emmc_250m_sel                  0        0        0    40000000          0     0  50000         N
          infra_msdc_hck              0        0        0    40000000          0     0  50000         N
       uart_sel                       1        1        0    40000000          0     0  50000         Y
          infra_uart0_sel             1        1        0    40000000          0     0  50000         Y
             infra_uart0              1        1        0    40000000          0     0  50000         Y
       spinfi_sel                     0        0        0    40000000          0     0  50000         N
          infra_spinfi1               0        0        0    40000000          0     0  50000         N
       top_rtc_32p7k                  0        0        0       32786          0     0  50000         Y
       top_rtc_32k                    0        0        0       32000          0     0  50000         Y
          infra_frtc                  0        0        0       32000          0     0  50000         N
       top_xtal_d2                    0        0        0    20000000          0     0  50000         Y
       sgmii0_tx250m_en               1        1        0    40000000          0     0  50000         Y
       sgmii0_rx250m_en               1        1        0    40000000          0     0  50000         Y
       sgmii0_cdr_ref                 1        1        0    40000000          0     0  50000         Y
       sgmii0_cdr_fb                  1        1        0    40000000          0     0  50000         Y
       sgmii1_tx250m_en               1        1        0    40000000          0     0  50000         Y
       sgmii1_rx250m_en               1        1        0    40000000          0     0  50000         Y
       sgmii1_cdr_ref                 1        1        0    40000000          0     0  50000         Y
       sgmii1_cdr_fb                  1        1        0    40000000          0     0  50000         Y
    apll2                             0        0        0   196608000          0     0  50000         Y
       aud_l_sel                      0        0        0   196608000          0     0  50000         N
          infra_aud_l                 0        0        0   196608000          0     0  50000         N
       top_apll2_d4                   0        0        0    49152000          0     0  50000         Y
          a_tuner_sel                 0        0        0    49152000          0     0  50000         N
             infra_aud_eg2            0        0        0    49152000          0     0  50000         N
          a1sys_sel                   0        0        0    49152000          0     0  50000         N
             infra_aud_aud            0        0        0    49152000          0     0  50000         N
    mpll                              3        3        0   416000000          0     0  50000         Y
       emmc_416m_sel                  0        0        0   416000000          0     0  50000         N
          infra_msdc                  0        0        0   416000000          0     0  50000         N
       top_mpll_d3_d2                 1        1        0    69333333          0     0  50000         Y
          sysapb_sel                  1        1        0    69333333          0     0  50000         Y
       top_mpll_d8_d2                 4        4        0    26000000          0     0  50000         Y
          u2u3_sel                    1        1        0    26000000          0     0  50000         Y
             infra_iusb               1        1        0    26000000          0     0  50000         Y
          csw_f26m_sel                1        1        0    26000000          0     0  50000         Y
             infra_ipcier             0        0        0    26000000          0     0  50000         N
             infra_adc_frc            0        0        0    26000000          0     0  50000         N
                infra_adc_26m         0        0        0    26000000          0     0  50000         N
             infra_therm              0        0        0    26000000          0     0  50000         N
             infra_sej_13m            0        0        0    26000000          0     0  50000         N
             infra_dramc_26m          0        0        0    26000000          0     0  50000         N
             infra_aud_26m            0        0        0    26000000          0     0  50000         N
             infra_uart2_sel          0        0        0    26000000          0     0  50000         Y
                infra_uart2           0        0        0    26000000          0     0  50000         N
             infra_uart1_sel          0        0        0    26000000          0     0  50000         Y
                infra_uart1           0        0        0    26000000          0     0  50000         N
          usb3_phy_sel                1        1        0    26000000          0     0  50000         Y
          pcie_phy_sel                0        0        0    26000000          0     0  50000         N
          dramc_sel                   1        1        0    26000000          0     0  50000         Y
          f_26m_adc_sel               0        0        0    26000000          0     0  50000         N
       top_mpll_d8                    0        0        0    52000000          0     0  50000         Y
       top_mpll_d4                    0        0        0   104000000          0     0  50000         Y
       top_mpll_d2                    1        1        0   208000000          0     0  50000         Y
          spim_mst_sel                0        0        0   208000000          0     0  50000         N
          spi_sel                     0        0        0   208000000          0     0  50000         N
             infra_spi1_sel           0        0        0   208000000          0     0  50000         Y
                infra_spi1            0        0        0   208000000          0     0  50000         N
             infra_spi0_sel           0        0        0   208000000          0     0  50000         Y
                infra_spi0            0        0        0   208000000          0     0  50000         N
          dramc_md32_sel              1        1        0   208000000          0     0  50000         Y
    net1pll                           4        4        0  2500000000          0     0  50000         Y
       top_net1pll_d8_d4              2        2        0    78125000          0     0  50000         Y
          ap2cnn_host_sel             1        1        0    78125000          0     0  50000         Y
          sgm_reg_sel                 1        1        0    78125000          0     0  50000         Y
       top_net1pll_d8_d2              1        1        0   156250000          0     0  50000         Y
          sysaxi_sel                  3        3        0   156250000          0     0  50000         Y
             infra_ipcieb             0        0        0   156250000          0     0  50000         N
             infra_iusb_133           1        1        0   156250000          0     0  50000         Y
             infra_msdc_133m          0        0        0   156250000          0     0  50000         N
             infra_trng               0        0        0   156250000          0     0  50000         N
             infra_aud_bus            0        0        0   156250000          0     0  50000         N
             infra_cq_dma             0        0        0   156250000          0     0  50000         N
             infra_sysaxi_d2          2        3        0    78125000          0     0  50000         Y
                infra_iusb_66m        1        1        0    78125000          0     0  50000         Y
                infra_msdc_66m        1        1        0    78125000          0     0  50000         Y
                infra_spi1_hck        0        0        0    78125000          0     0  50000         N
                infra_spi0_hck        0        0        0    78125000          0     0  50000         N
                infra_nfi_hck         0        0        0    78125000          0     0  50000         N
                infra_sej             0        0        0    78125000          0     0  50000         N
                infra_ap_dma          0        1        0    78125000          0     0  50000         N
                infra_dbg             0        0        0    78125000          0     0  50000         N
                infra_pwm_hck         0        0        0    78125000          0     0  50000         N
                infra_gpt_sta         0        0        0    78125000          0     0  50000         N
          pwm_sel                     0        0        0   156250000          0     0  50000         N
             infra_pwm_bsel           0        0        0   156250000          0     0  50000         Y
                infra_pwm_sta         0        0        0   156250000          0     0  50000         N
             infra_pwm2_sel           0        0        0   156250000          0     0  50000         Y
                infra_pwm2            0        0        0   156250000          0     0  50000         N
             infra_pwm1_sel           0        0        0   156250000          0     0  50000         Y
                infra_pwm1            0        0        0   156250000          0     0  50000         N
       top_net1pll_d5_d4              2        3        0   125000000          0     0  50000         Y
          u2u3_xhci_sel               1        1        0   125000000          0     0  50000         Y
          u2u3_sys_sel                1        1        0   125000000          0     0  50000         Y
             infra_iusb_sys           1        1        0   125000000          0     0  50000         Y
          pextp_tl_ck_sel             0        0        0   125000000          0     0  50000         N
             infra_ipcie              0        0        0   125000000          0     0  50000         N
             infra_pcie_sel           0        0        0   125000000          0     0  50000         Y
          i2c_sel                     0        1        0   125000000          0     0  50000         N
             infra_i2c0               0        1        0   125000000          0     0  50000         N
       top_net1pll_d5_d2              0        0        0   250000000          0     0  50000         Y
       top_net1pll_d5                 1        1        0   500000000          0     0  50000         Y
          netsys_500m_sel             1        1        0   500000000          0     0  50000         Y
       top_net1pll_d4                 0        0        0   625000000          0     0  50000         Y
    wedmcupll                         1        1        0   760000000          0     0  50000         Y
       netsys_mcu_sel                 2        2        0   760000000          0     0  50000         Y
          eth_wocpu1_en               1        1        0   760000000          0     0  50000         Y
          eth_wocpu0_en               1        1        0   760000000          0     0  50000         Y
       top_wedmcupll_d5_d2            0        0        0    76000000          0     0  50000         Y
    sgmpll                            1        1        0   325000000          0     0  50000         Y
       sgm_325m_sel                   2        2        0   325000000          0     0  50000         Y
          eth_gp2_en                  1        1        0   325000000          0     0  50000         Y
          eth_gp1_en                  1        1        0   325000000          0     0  50000         Y
    mmpll                             3        3        0  1440000000          0     0  50000         Y
       top_mmpll_u2phy                2        2        0    48000000          0     0  50000         Y
          da_u2_ck_1p_sel             2        2        0    48000000          0     0  50000         Y
          da_u2_refsel                2        2        0    48000000          0     0  50000         Y
       top_mmpll_d3_d8                0        0        0    60000000          0     0  50000         Y
       top_mmpll_d8_d2                0        0        0    90000000          0     0  50000         Y
       top_mmpll_d8                   0        0        0   180000000          0     0  50000         Y
          nfi1x_sel                   0        0        0   180000000          0     0  50000         N
             infra_fbist2fpc          0        0        0   180000000          0     0  50000         N
             infra_nfi1               0        0        0   180000000          0     0  50000         N
       top_mmpll_d4                   1        1        0   360000000          0     0  50000         Y
          netsys_sel                  1        1        0   360000000          0     0  50000         Y
       top_mmpll_d2                   1        1        0   720000000          0     0  50000         Y
          conn_mcusys_sel             1        1        0   720000000          0     0  50000         Y
    net2pll                           1        1        0   800000000          0     0  50000         Y
       eip_b_sel                      0        0        0   800000000          0     0  50000         N
          infra_eip97                 0        0        0   800000000          0     0  50000         N
       netsys_2x_sel                  1        1        0   800000000          0     0  50000         Y
          eth_fe_en                   1        1        0   800000000          0     0  50000         Y
       top_net2pll_d3_d2              0        0        0   400000000          0     0  50000         Y
          arm_db_main_sel             0        0        0   400000000          0     0  50000         N
       top_net2pll_d4_d2              0        0        0   100000000          0     0  50000         Y
       top_net2pll_d4                 0        0        0   200000000          0     0  50000         Y
    armpll                            1        1        0  2000000000          0     0  50000         Y

The clock already moved to mpll

Edit:

I think now that you meant to add the parent, and not to add the rate. I will try it like this:

&mmc0 {
		assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
						  <&topckgen CLK_TOP_EMMC_250M_SEL>;
		assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
								 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
};

Last edit:

This works. According to /sys/kernel/debug/clk/clk_summary there is no difference when booting with or without U-Boot. Also using HS400, there are no more errors.

@sam33 is this the right way to add these 2 properties to mt7986.dtsi?

I think this is what he meant, as it is the kernel version of:

u-boot/arch/arm/dts/mt7986.dtsi at 50842b217fef505a0ec6662cc2acdc55d0bb23c5 · u-boot/u-boot (github.com)

On U-Boot:

		assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
				  <&topckgen CK_TOP_EMMC_250M_SEL>;
		assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
					 <&topckgen CK_TOP_NET1_D5_D2>;

I think it’s fine.
Thank you both for your help and testing!