Hereās the DTS nodes as per the patches originally released by ryder lee? canāt remember where I got them from :
g3dsys: clock-controller@13000000 {
compatible = "mediatek,mt7623-g3dsys",
"mediatek,mt2701-g3dsys",
"syscon";
reg = <0 0x13000000 0 0x200>;
#clock-cells = <1>;
#reset-cells = <1>;
};
larb3: larb@13010000 {
compatible = "mediatek,mt7623-smi-larb",
"mediatek,mt2701-smi-larb";
reg = <0 0x13010000 0 0x1000>;
mediatek,smi = <&smi_common>;
mediatek,larb-id = <3>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "apb", "smi";
power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
};
mali: gpu@13040000 {
compatible = "mediatek,mt7623-mali", "arm,mali-450";
reg = <0 0x13040000 0 0x30000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1", "pp2", "ppmmu2", "pp";
clocks = <&topckgen CLK_TOP_MMPLL>, <&g3dsys CLK_G3DSYS_CORE>;
clock-names = "bus", "core";
power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
mediatek,larb = <&larb3>;
resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
};
I donāt know if this is correct. Other Mali450 boards list a āpmuā interrupt which is also required by the official mali kernel driver. Note the SPI āaddressā goes from 177 to 180 - Iāve seen other MP4 boards list āpp3ā and āppmmu3ā interrupts - which makes sense given the Mali 450 MP4 (which is apparently on the R2) is supposed to have 8 pp units and thereās a gap of two in that list. Letās be clear - I have no idea whatsoever if this entry is correct and I do suspect that itās incomplete. Iāve been through all of the documentation I have including the datasheets but I couldnāt find anything pertaining to how the mali450 is implemented here. These DTS entries are all we have to go on right now.
also larb3 needs adding to iommu :
iommu: mmsys_iommu@10205000 {
compatible = "mediatek,mt7623-m4u",
"mediatek,mt2701-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
#iommu-cells = <1>;
};