i guessed he meant via gpio-lib/sysfs setting this gpio to low…at hardware layer imho it is hard to access (especially when board is running) without shorting anything else (once i know the pads to do this)
Well, it is not that hard if you have the right tools. It is a development board for a reason.
I was hoping that this is a fix to mend the horrible signal to noise ratio degradation when SFP is not populated, but it seems the core PCB design remains same. Yes I am ranting here, because you could simply look at AsiaRF board design and take some notes and learn. High speed signal routing, ESD protection measures and heat management, just copy, paste, but oh well…
BTW I just retired my BPI-R4 due to various device quirks. I still use BPI-R3 as it holds pretty well, besides the bug you cannot plug 100Gb device to the switch part, it still stalls making it dog slow.