I can build you an image. Do you want me to use the bpi github or the master branch? What packages do you need?
This one:
I need an sdcard image for bpi R4, with target defaults, pci-utils and pciids, that’s all, actually (but usb-utils and usbids would also be nice)
Thx. I sent you access request
Maybe you can make this file/folder public? This lets others use the image too and help getting this pcie working?
I thought it was public. Should be fixed.
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I’m very interested in the m2 B key slot so I’ll help any way I can. I can always create a proper build environment for you and give you shell access. My build system is an i9-14900k, 7000mb read/write nvme, 48 gigs of 7400mhz, and 940mb up/down. I have 48 more to put in it but having trouble getting 96gb to run stable at 7400mhz.
Tomorrow I plan on starting to work on this issue with the PCIe2 slot. To begin trouble shooting this issue I’m going to be using the same X55 card. Could you tell me what firmware or modules that card needs? I’ve searched online but am unable to find anything clear about it. The fact that I can’t find much on it I’m assuming that it’s just built into the kernel already?
If you are planning to use OpenWrt you will need kernel modules for support of MHI PCIe device as well as ModemManager to be able to use the modem (uqmi doesn’t work yet with the X55)
kmod-mhi-net
kmod-mhi-wwan-ctrl
modemmanager
In order to diagnose whether PCIe 2 is working or not you won’t need any of that – right now the link doesn’t come up and you can clearly see that in the bootlog and as long as that is the case (supposedly because a clock or PHY hasn’t been setup correctly) that’s what you are going to be stuck with and having drivers installed or not anyway doesn’t make a difference at this point.
thank you for the fast reply
@dangowrt : how did you activate the pci bus with the sinovoip image? using @HighVoltage86’s image I still get the error:
[ 1.671960] mtk-pcie 11280000.pcie: host bridge /pcie@11280000 ranges:
[ 1.678571] mtk-pcie 11280000.pcie: Parsing ranges property...
[ 1.684485] mtk-pcie 11280000.pcie: IO 0x20000000..0x201fffff -> 0x20000000
[ 1.691805] mtk-pcie 11280000.pcie: MEM 0x20200000..0x27ffffff -> 0x20200000
[ 1.699138] mtk-xsphy usb-phy@11e10000: incompatible phy type
[ 1.704979] mtk-pcie 11280000.pcie: failed to get max link width
[ 1.918333] mtk-pcie 11280000.pcie: PCIe link down, ltssm reg val: 0x3000003
so, what did you do to activate it?
Are you sure he was using the M76 version of Sinovoip’s github?
Maybe this one instead?
“GitHub - BPI-SINOVOIP/BPI-R4-OPENWRT-V21.02”
Just in case I built that image as well. So below is built images of both of his branches.
thx … didn’t work out either. Maybe dangowrt could tell us what he exactly did.
lspci reports the following
0003:00:00.0 PCI bridge: MEDIATEK Corp. Device 7988 (rev 01) (prog-if 00 [Normal decode])
Flags: fast devsel
Memory at 20300000 (64-bit, non-prefetchable) [disabled] [size=32K]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: [disabled] [32-bit]
Memory behind bridge: 20200000-202fffff [size=1M] [32-bit]
Prefetchable memory behind bridge: [disabled] [64-bit]
Capabilities: [80] Express Root Port (Slot-), MSI 00
Capabilities: [e0] MSI: Enable- Count=1/32 Maskable+ 64bit+
Capabilities: [f8] Power Management version 3
Capabilities: [100] Vendor Specific Information: ID=1556 Rev=1 Len=008 <?>
Capabilities: [110] L1 PM Substates
Capabilities: [200] Advanced Error Reporting
Capabilities: [300] Secondary PCI Express
0003:01:00.0 Unassigned class [ff00]: Foxconn International, Inc. Device e0af
Subsystem: Qualcomm Device 010c
Flags: fast devsel
Memory at 20200000 (64-bit, non-prefetchable) [disabled] [size=4K]
Memory at 20201000 (64-bit, non-prefetchable) [disabled] [size=4K]
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/32 Maskable+ 64bit+
Capabilities: [70] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] Secondary PCI Express
Capabilities: [168] Physical Layer 16.0 GT/s <?>
Capabilities: [18c] Lane Margining at the Receiver <?>
Capabilities: [19c] Transaction Processing Hints
Capabilities: [228] Latency Tolerance Reporting
Capabilities: [230] L1 PM Substates
Capabilities: [240] Data Link Feature <?>This is using the image off of the getting started wiki. It’s the only image so far that has recognized the device at all.
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dmesg as well
[ 1.100878] mtk-pcie 11280000.pcie: host bridge /pcie@11280000 ranges:
[ 1.107493] mtk-pcie 11280000.pcie: Parsing ranges property...
[ 1.113400] mtk-pcie 11280000.pcie: IO 0x20000000..0x201fffff -> 0x20000000
[ 1.120719] mtk-pcie 11280000.pcie: MEM 0x20200000..0x27ffffff -> 0x20200000
[ 1.128046] mtk-xsphy usb-phy@11e10000: incompatible phy type
[ 1.133885] mtk-pcie 11280000.pcie: failed to get max link width
[ 1.273984] mtk-pcie 11280000.pcie: PCI host bridge to bus 0003:00
[ 1.280247] pci_bus 0003:00: root bus resource [bus 00-ff]
[ 1.285805] pci_bus 0003:00: root bus resource [io 0x400000-0x5fffff] (bus address [0x20000000-0x201fffff])
[ 1.295759] pci_bus 0003:00: root bus resource [mem 0x20200000-0x27ffffff]
[ 1.302718] pci_bus 0003:00: scanning bus
[ 1.306784] pci 0003:00:00.0: [14c3:7988] type 01 class 0x060400
[ 1.312883] pci 0003:00:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]
[ 1.319806] pci 0003:00:00.0: PME# supported from D0 D3hot D3cold
[ 1.325979] pci 0003:00:00.0: PME# disabled
[ 1.331074] pci_bus 0003:00: fixups for bus
[ 1.335308] pci 0003:00:00.0: scanning [bus 00-00] behind bridge, pass 0
[ 1.342091] pci 0003:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 1.350201] pci 0003:00:00.0: scanning [bus 00-00] behind bridge, pass 1
[ 1.357030] pci_bus 0003:01: scanning bus
[ 1.361107] pci 0003:01:00.0: [105b:e0af] type 00 class 0xff0000
[ 1.367221] pci 0003:01:00.0: reg 0x10: [mem 0x00000000-0x00000fff 64bit]
[ 1.374107] pci 0003:01:00.0: reg 0x18: [mem 0x00000000-0x00000fff 64bit]
[ 1.381087] pci 0003:01:00.0: PME# supported from D0 D3hot D3cold
[ 1.387256] pci 0003:01:00.0: PME# disabled
[ 1.391503] pci 0003:01:00.0: 7.876 Gb/s available PCIe bandwidth, limited by 8 GT/s x1 link at 0003:00:00.0 (capable of 31.506 Gb/s with 16 GT/s x2 link)
[ 1.406318] pci_bus 0003:01: fixups for bus
[ 1.410555] pci_bus 0003:01: bus scan returning with max=01
[ 1.416196] pci_bus 0003:01: busn_res: [bus 01-ff] end is updated to 01
[ 1.422894] pci_bus 0003:00: bus scan returning with max=01
[ 1.428538] pci 0003:00:00.0: BAR 8: assigned [mem 0x20200000-0x202fffff]
[ 1.435415] pci 0003:00:00.0: BAR 0: assigned [mem 0x20300000-0x20307fff 64bit]
[ 1.442821] pci 0003:01:00.0: BAR 0: assigned [mem 0x20200000-0x20200fff 64bit]
[ 1.450235] pci 0003:01:00.0: BAR 2: assigned [mem 0x20201000-0x20201fff 64bit]
[ 1.457644] pci 0003:00:00.0: PCI bridge to [bus 01]
[ 1.462669] pci 0003:00:00.0: bridge window [mem 0x20200000-0x202fffff]
[ 1.469552] pci 0003:00:00.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 256
[ 1.478109] pci 0003:01:00.0: Max Payload Size set to 256/ 256 (was 128), Max Read Rq 256In this software it thinks its on 0003. Also it doesn’t say mtk pci gen 3 only mtk-pcie. Makes me think driver issue?
I can’t do anything with that because they didn’t release their build script. I can’t even build the modules needed to make the 5g module work because of that. If they did I could work on finding the differences between their initial release builds and everyone else’s. If anyone knows anyone at BPI that could give us that info would be nice.
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indeed … there’s something strange about the DTS file though: the pcie controller points to a usb phy (which is normal because it’s actually a shared usb / pcie phy), but that phy driver (xsphy) is not specifying any compatibility with PCIe. we must be missing something here
If you look at the code you will see that the driver in SinoVoip tree just always emits that error (incompatible phy type) even if the PCIe is setup correctly. Also I can confirm that Snapdragon X55-based modem gets detected with SinoVoip stock firmware.
Were you able to get it working?
So despite having tried multiple adapters to mini pcie devices which worked at bus 0 and 1, it didn’t come up. Glad that’s sorted out, but too bad it doesn’t work 