How to get IRQ number for GPIO?

Banana Pi SBCs design BPI-M3(A83T/R18)
1

I have written Linux driver that works fine on Raspberry Pi. Now I am trying to make it work on BPI-M3. To make the story short I will skip details about my fight to compile and load the driver. I’ve solved these quests. The current problem happens during initialization of the driver. Basically function gpio_to_irq(gpio) does not work. So, the question is how to get IRQ number for GPIO to setup interruption handler? Of course I have already tried to look at sources but still have no clue why it does not work.

A little bit more details. I am trying to get IRQ for GPIO 71. Is it a valid GPIO number? I think this is the GPIO on pin 13.

And one more question (yes, I am so naive): where can I get the real sources or headers for the kernel? I know about https://github.com/BPI-SINOVOIP/BPI-M3-bsp.git but I see differences in checksums in some modules.

2

gpio define :

https://bananapi.gitbooks.io/bpi-m3/content/en/bpi-m3_gpio_pin_define.html

3

Do you mean that this GPIO number is 27 and it is the same as on RPI? Then what numbers we see in output of the command gpio readall ?

4

Update: GPIO 27 is not valid. gpio_request() returns -EINVAL. But for 71 gpio_request and gpio_direction_input executed without errors. This is the reason why I think that 71 is a valid GPIO number for pin 13.

So, the question is the same: how to get IRQ number if gpio_to_irq does not work?

5

please see Allwinner_A83T_User_Manual_V1.5.1 documents:

https://drive.google.com/file/d/0B4PAo2nW2KfnRjlQaU9uR0J0elE/view?usp=sharing

7

Do you really think it is helpful? I was expecting an answer about software rather than hardware.

Actually I think I am close to the answer but some real help would be very appreciated.

First of all, I was right about gpio 71 on pin 13.

GPIO#71 is PC7 = SUNXI_PC_BASE+7 = 64+7 = 71.

For anybody else who will look for the same information: looks like command gpio readall shows correct gpio numbers in columns CPU. The source code where you can find useful information about GPIOs ( see https://github.com/BPI-SINOVOIP/BPI-M3-bsp ):

  • linux-sunxi/arch/arm/mach-sunxi/include/mach/pinctrl.h defines base numbers for banks (in my case SUNXI_PC_BASE=64).

  • linux-sunxi/drivers/pinctrl/pinctrl-sun8iw6.c defines GPIO banks:

    static struct sunxi_pin_bank sun8i_w6_banks[] = { SUNXI_PIN_BANK(SUNXI_PIO_VBASE, SUNXI_PB_BASE, 11, SUNXI_EINT_TYPE_GPIO, "PB", SUNXI_IRQ_EINTB), SUNXI_PIN_BANK(SUNXI_PIO_VBASE, SUNXI_PC_BASE, 19, SUNXI_EINT_TYPE_NONE, "PC", SUNXI_IRQ_MAX ), SUNXI_PIN_BANK(SUNXI_PIO_VBASE, SUNXI_PD_BASE, 24, SUNXI_EINT_TYPE_NONE, "PD", SUNXI_IRQ_MAX ), SUNXI_PIN_BANK(SUNXI_PIO_VBASE, SUNXI_PE_BASE, 20, SUNXI_EINT_TYPE_NONE, "PE", SUNXI_IRQ_MAX ), SUNXI_PIN_BANK(SUNXI_PIO_VBASE, SUNXI_PF_BASE, 7, SUNXI_EINT_TYPE_NONE, "PF", SUNXI_IRQ_MAX ), SUNXI_PIN_BANK(SUNXI_PIO_VBASE, SUNXI_PG_BASE, 14, SUNXI_EINT_TYPE_GPIO, "PG", SUNXI_IRQ_EINTG), SUNXI_PIN_BANK(SUNXI_PIO_VBASE, SUNXI_PH_BASE, 12, SUNXI_EINT_TYPE_GPIO, "PH", SUNXI_IRQ_EINTH), SUNXI_PIN_BANK(SUNXI_R_PIO_VBASE, SUNXI_PL_BASE, 13, SUNXI_EINT_TYPE_GPIO, "PL", SUNXI_IRQ_EINTL), };

As we can see it specifies irq SUNXI_IRQ_MAX for PC bank.

  • linux-sunxi/drivers/pinctrl/pinctrl-sunxi.h defines the macros SUNXI_PIN_BANK:

`

 #define SUNXI_PIN_BANK(_mem_base, _pin_base, _number, _eint_type, _name, _irq)\
        {                            \
         .membase = (void __iomem *)_mem_base,        \
         .pin_base = _pin_base,                \
         .nr_pins  = _number,                \
         .eint_type = _eint_type,            \
         .name     = _name,                \
         .irq      = _irq,                \
        }

`

  • linux-sunxi/arch/arm/mach-sunxi/include/mach/sun8i/irqs-sun8iw6p1.h:

    #define SUNXI_IRQ_MAX (SUNXI_GIC_START + 256)

  • linux-sunxi/drivers/pinctrl/pinctrl-sunxi.c contains implementation of functions that I need but it is not clear how to call it and why it does not work through gpio_to_irq.

8

Well, I know the answer to my question. But I am really disappointed by bpi team support. Why did you not answer correctly to this simple technical question?

The answer. Not all GPIO pins support interruptions. Basically, this is hardware limitation. Only CPU pins from PB, PG, PH and PL banks have interrupts. The ranges of CPU pin numbers: 32…42, 192…205, 224…235, 352…365. Now look at output of command “gpio readall”. Obviously not all pins on GPIO connector of BPI-M3 are in these ranges. That is the reason why you cannot set interruption handler for these pins.

9

BTW, Now I have a driver that allows to receive data from RF 433MHz receivers on BPI-M3. If somebody want to look at it right now then you can find it here: https://github.com/alex-konshin/gpio-ts Currently I have no good instructions or even description. I spent most of my free time on this damn BPI-M3 because my question was not answered. I will try to update my projects on github during next week. I will also provide the compiled driver because I know the pain of building anything for BPI-M3 kernel.