[BPI-R2] Hdmi in uboot and linux

Banana Pi BPI-R4/BPI-R3 Mini/BPI-R3/BPI-R64/BPI-R2
61

Did you changed anything? Have you seen hsync anywhere?

Have you used 1024x768 over dvi or vga? I tested this and below only with vga-adapter (wich is working with rpi)

62

Nothing since my last pull request.

It’s 60kHz New photo by Alexander Ryabchenko

63

It’s hdmi. Recently i got hdmi to VGA adapter, but haven’t yet tested it.

64

Which timers do you mean? setup_timer => init_timer? The reversed way we’ve done for internal wifi-driver…maybe it helps you on porting

i have only my tv with hdmi-input…one monitor with dvi (1280x1024) and the one with vga (1024x768)

65

I mean clocks, in general: dts-files, clock drivers in ./drivers/clk/mediatek/* , unless i undestood this stuff, i would not to propertly regognize causes of these problems. For now i’m looking for info, so if someone know what to start from i’ll be very appreciative :slight_smile:

1.The hdmi port is seems to be detected and enabled, but there is no output signal, probably the problem is caused by wrong clock frequency.

  1. there are errors in dmesg like:

     [   41.691319] CPU: 0 PID: 980 Comm: mtk_wmtd Tainted: G           O    4.14.43-bpi-r2-hdmi #9
 [   41.691321] Hardware name: Mediatek Cortex-A7 (Device Tree)
 [   41.691325] task: ddbb3600 task.stack: dcc70000
 [   41.691338] PC is at regulator_set_mode+0x18/0xb4
 [   41.691346] LR is at mtk_wcn_consys_hw_reg_ctrl+0x118/0x68c
 [   41.691350] pc : [<c045f4bc>]    lr : [<c054ea78>]    psr: 60020013
 [   41.691353] sp : dcc71d70  ip : dcc71d98  fp : dcc71d94
 [   41.691356] r10: c1006da0  r9 : 00000001  r8 : 00000001
 [   41.691364] r7 : 00000000  r6 : c0f582f0  r5 : c1049ea8  r4 : c0f9e118
 [   41.691374] r3 : c0e9f3d8  r2 : 00000000  r1 : 00000008  r0 : 00000000
 [   41.691386] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
 [   41.691393] Control: 10c5387d  Table: 9cf1c06a  DAC: 00000051
 [   41.691400] Process mtk_wmtd (pid: 980, stack limit = 0xdcc70218)
 [   41.691409] Stack: (0xdcc71d70 to 0xdcc72000)
 [   41.691426] 1d60:                                     00000002 dcc71d8c dcc71dd4 c0f9e118
 [   41.691437] 1d80: c1049ea8 c0f582f0 dcc71dd4 dcc71d98 c054ea78 c045f4b0 0000007d c0f03ca0
 [   41.691445] 1da0: dcc71e14 de83cb40 00000000 c0f582f0 00000000 c10060ec 00000000 00000000
 [   41.691453] 1dc0: 00000001 c1006da0 dcc71dec dcc71dd8 c054f1a0 c054e96c c0f582dc c0f9e520
 [   41.691461] 1de0: dcc71e04 dcc71df0 c0550f58 c054f15c dcc71eb4 dcc71eb0 dcc71e14 dcc71e08
 [   41.691471] 1e00: c052d8ec c0550ec4 dcc71e24 dcc71e18 c052d9d8 c052d890 dcc71ea4 dcc71e28
 [   41.691496] 1e20: c0529f2c c052d9a0 c0ea3cc0 c0159f6c 00000000 c0148ffc ffffffff 00000001
 [   41.691511] 1e40: 00000000 00000000 c0148ffc c0112c18 c0f00018 ddbb3600 00000000 c0f07380
 [   41.691535] 1e60: dcf61c00 c0f07380 df5a2cc0 ddbb3600 00000000 dcf61c00 c0ea3cc0 ddbb3978
 [   41.691547] 1e80: 00000002 c0a4b830 c10060ec c0c2f508 c0c43bfc c0c31460 dcc71ee4 dcc71ea8
 [   41.691570] 1ea0: c052beec c0529eec 1e6ff000 c0c2f54c 00000000 00000000 dcc71eec c10060ec
 [   41.691585] 1ec0: 00000000 c100669c c1006da0 c0530b34 c1049e78 c10066b8 dcc71f14 dcc71ee8
 [   41.691605] 1ee0: c052c0e0 c052be74 c0530b34 c10066b8 dcc71f34 c1006da0 c1006674 c100669c
 [   41.691624] 1f00: dcc70000 c0530b34 dcc71f24 dcc71f18 c0529e54 c052c090 dcc71f34 dcc71f28
 [   41.691632] 1f20: c0529ea0 c0529e2c dcc71f74 dcc71f38 c0533200 c0529e80 c0c35480 c0c354ec
 [   41.691655] 1f40: c0c354a8 00000000 dcffe59c dcffe580 00000000 dcffe000 dcc70000 c1006674
 [   41.691670] 1f60: dcffe59c dcf23dd0 dcc71fac dcc71f78 c0147600 c053306c 00000000 c0533060
 [   41.691678] 1f80: dcc71fac dcffe000 c01474bc 00000000 00000000 00000000 00000000 00000000
 [   41.691697] 1fa0: 00000000 dcc71fb0 c0108e88 c01474c8 00000000 00000000 00000000 00000000
 [   41.691714] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
 [   41.691721] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
 [   41.691753] [<c045f4bc>] (regulator_set_mode) from [<c054ea78>] (mtk_wcn_consys_hw_reg_ctrl+0x118/0x68c)
 [   41.691768] [<c054ea78>] (mtk_wcn_consys_hw_reg_ctrl) from [<c054f1a0>] (mtk_wcn_consys_hw_pwr_on+0x50/0xc4)
 [   41.691779] [<c054f1a0>] (mtk_wcn_consys_hw_pwr_on) from [<c0550f58>] (wmt_plat_pwr_ctrl+0xa0/0x124)
 [   41.691792] [<c0550f58>] (wmt_plat_pwr_ctrl) from [<c052d8ec>] (wmt_ctrl_hw_pwr_on+0x68/0x88)
 [   41.691814] [<c052d8ec>] (wmt_ctrl_hw_pwr_on) from [<c052d9d8>] (wmt_ctrl+0x44/0xc0)
 [   41.691836] [<c052d9d8>] (wmt_ctrl) from [<c0529f2c>] (wmt_core_ctrl+0x4c/0xcc)
 [   41.691860] [<c0529f2c>] (wmt_core_ctrl) from [<c052beec>] (opfunc_pwr_on+0x84/0x21c)
 [   41.691875] [<c052beec>] (opfunc_pwr_on) from [<c052c0e0>] (opfunc_func_on+0x5c/0x348)
 [   41.691898] [<c052c0e0>] (opfunc_func_on) from [<c0529e54>] (wmt_core_opid_handler+0x34/0x54)
 [   41.691921] [<c0529e54>] (wmt_core_opid_handler) from [<c0529ea0>] (wmt_core_opid+0x2c/0x6c)
 [   41.691941] [<c0529ea0>] (wmt_core_opid) from [<c0533200>] (wmtd_thread+0x1a0/0x254)
 [   41.691961] [<c0533200>] (wmtd_thread) from [<c0147600>] (kthread+0x144/0x174)
 [   41.691983] [<c0147600>] (kthread) from [<c0108e88>] (ret_from_fork+0x14/0x2c)
 [   41.692004] Code: e24cb004 e24dd00c e52de004 e8bd4000 (e5904030) 
 [   41.692029] ---[ end trace b3b93c8cbd6e140d ]---

  2. R2 dont reboots on reboot command

    [ 2144.497906] reboot: Restarting system [ 2145.501566] Reboot failed – System halted

66

seems to be from wifi-driver… consys is the 4-in-1 chip for wifi,bt and other

try to disable the consys-part in defconfig…

CONFIG_MTK_COMBO=y
CONFIG_MTK_COMBO_CHIP_CONSYS_7623=y
CONFIG_MTK_COMBO_COMM=y
CONFIG_MTK_COMBO_WIFI=y
CONFIG_BT=y
CONFIG_MTK_COMBO_BT=y
CONFIG_MTK_COMBO_BT_HCI=y

i don’t know if the wifi-driver was working in 4.14 at time of creating the branch…

sure to remove that?

compatible = "mediatek,mt7623-pinctrl";
67

Can i set hsync manually anywhere? How? Or at least print calculated value…i have not seen it in drm-logs

68

Imho, hsync is depends on other parameters: resolution and refresh rate, so You can’t define it directly.

69

There must be a calculation or definition which seems to be wrong (for some monitors). currently it is the only parameter which causes trouble in my eyes

70

I’ve built working 4.14 kernel: without WiFi/BT and with defconfig imported from 4.16-hdmi. It looks good: both fbdev and Xorg are Ok, but it’s not able to reeboot, halts on:

[ 252.851527] reboot: Restarting system

71

I’ve commited all changes to https://github.com/d3adme4t/BPI-R2-4.14/tree/4.14-hdmi

72

Can you try to create a new branch from 4.14-main and merge your changes there? Maybe it’s a problem in hdmi-branch

Btw. I understand, that i cannot use every value for hsync…but i want to apply the values from my screenshots (working values on rpi)

73

That is exactly that i’ve done. I’ve created new branch from 4.14-main, and then i’ve applied patches from 4.16-hdmi trying to adapt them for 4.14. I can repeat this process, but i think result will be the same.

Or, may be, I just misunderstood Your plan :slight_smile:

74

I thought you used existing 4.14-hdmi…ok it is named only hdmi

Reboot/shutdown should depend on watchdog,pmic and rtc mt63xx

75

I’ve found a VGA calculator, the results seems to be correct, at least for my modes. http://www.epanorama.net/faq/vga2rgb/calc.html

My hypothesis is that in Your case hdmi/drm driver can’t communicate with TV/monitor propertly, and can’t choose proper mode. There are mentions about hsync in mtk_hdmi.c , mtk_dpi.c and mtk_dsi.c. Probably You would add some additional debug message to check them, or even trace the code where it’s calculated.

76

Have you tried with 60hz vsync (1024x768,800x600,640x480)?

I’m not an expert in display-calculation,but if monitor+adapter works with rpi it also should work with r2

Where should i place printks to show hsync?

What about edid-files i’ve mentioned above?

77

For what resolution?

78

I didn’t found it yet, i need to review the code.

79

Do you mean https://github.com/frank-w/BPI-R2-4.14/tree/4.16-hdmi/Documentation/EDID? if so - #define CLOCK 40000 /* kHz */ is not hsync it’s probably pixel clock, and it’s in 40MHz, not 40kHz

80

right…i thought the comment is meant “value should be in kHz”…800x600 is the only resolution that shows anything on my screen (but not readable)…for the other resolutions there are no edid-files…but it’s in documentation folder so i guess its not compiled in kernel

so i need a way to set hsync anyhow…or at least read it out in running system

for reboot-problem…have you tried “debug=7” option in cmdline? have you same problem with 4.16?

Can you try vga-calc with 60hz vsync (1024x768,800x600,640x480)? i do not know porch and sync-pulse values…vertical sync pulse should be 60 (hz) right? but it needs also the horizontal sync which i want to get

in mtk_hdmi.c line 1380:

        dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
            adjusted_mode->hsync_start, adjusted_mode->hsync_end,
            adjusted_mode->htotal);

shouldn*t i get this with drm.debug-option?